Have basic Low Speed SWIM read on the fly working.
Only reads one byte, but good enough.. to get things done. Code should actually work for low and high speed, but have only tested high speed on writes so far. Having issue where reads can fail at times. Esp with long strings of '0'.. Perhaps operating at high speed would improve matters.. Although I'm also realizing maybe I'm not waiting for the device to reset and reload HSI trim factory value, need to check that.. The new assembly file/function does everything needed so can start cutting out inline assembly from swim_out function. Swim code needs to run at 48Mhz. Realizing this is pretty vital to having enough time to handle high speed. And timing of artificial pull-up requires high trimmability..
This commit is contained in:
Paul Molloy
parent
0e0e307f64
commit
49b4639aa4
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@ -65,6 +65,8 @@ CFLAGS+= $(DEFINE) $(INCLUDE)
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SOURCES=$(wildcard source/*.c source_stm_only/*.c)
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OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
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ASM_SRC=$(wildcard source/asm_stm/*.s)
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#all: dir shared $(BUILD)/$(PROJ).axf $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
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all: dir shared $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
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@ -72,10 +74,10 @@ all: dir shared $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin s
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# $@ is shortcut for the target, $^ is shortcut for prereqs
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# TARGET: PREREQS
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$(BUILD)/$(PROJ).axf: $(STARTUP) $(OBJECTS)
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$(CC) $^ $(CFLAGS) $(LFLAGS) -o $@
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$(CC) $^ $(ASM_SRC) $(CFLAGS) $(LFLAGS) -o $@
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$(BUILD)/$(PROJ).elf: $(STARTUP) $(OBJECTS)
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$(CC) $^ $(CFLAGS) $(LFLAGS) -o $@
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$(CC) $^ $(ASM_SRC) $(CFLAGS) $(LFLAGS) -o $@
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$(BUILD)/$(PROJ).hex: $(BUILD)/$(PROJ).elf
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$(OBJCOPY) -O ihex $^ $@
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@ -23,6 +23,7 @@ BASE=.
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# Compiler & Linker
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CC=arm-none-eabi-gcc
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ASM=arm-none-eabi-as
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CXX=arm-none-eabi-g++
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OBJCOPY=arm-none-eabi-objcopy
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SIZE=arm-none-eabi-size
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@ -31,7 +32,7 @@ SIZE=arm-none-eabi-size
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ARCH_FLAGS=-mthumb -mcpu=cortex-m$(CORTEX_M)
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# Startup code
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STARTUP=$(BASE)/include_stm/startup_ARM$(CORE).S
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STARTUP=$(BASE)/include_stm/startup_ARM$(CORE).S
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# -Os -flto -ffunction-sections -fdata-sections to compile for code size
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CFLAGS=$(ARCH_FLAGS) $(STARTUP_DEFS) -Os -flto -ffunction-sections -fdata-sections -g
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@ -61,21 +62,23 @@ DEFINE+=\
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INCLUDE=-I ./include_stm
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CFLAGS+= $(DEFINE) $(INCLUDE)
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#SOURCES=$(wildcard source/**/*.c source/*.c)
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SOURCES=$(wildcard source/*.c source_stm_only/*.c)
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OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
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ASM_SRC=$(wildcard source/asm_stm/*.s)
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#all: dir shared $(BUILD)/$(PROJ).axf $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
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all: dir shared $(BUILD)/$(PROJ).elf $(BUILD)/$(PROJ).hex $(BUILD)/$(PROJ).bin size
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#build axf file output (basically elf with DWARF debug info)
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# $@ is shortcut for the target, $^ is shortcut for prereqs
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# TARGET: PREREQS
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$(BUILD)/$(PROJ).axf: $(STARTUP) $(OBJECTS)
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$(CC) $^ $(CFLAGS) $(LFLAGS) -o $@
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$(CC) $^ $(ASM_SRC) $(CFLAGS) $(LFLAGS) -o $@
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$(BUILD)/$(PROJ).elf: $(STARTUP) $(OBJECTS)
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$(CC) $^ $(CFLAGS) $(LFLAGS) -o $@
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$(CC) $^ $(ASM_SRC) $(CFLAGS) $(LFLAGS) -o $@
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$(BUILD)/$(PROJ).hex: $(BUILD)/$(PROJ).elf
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$(OBJCOPY) -O ihex $^ $@
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@ -0,0 +1,514 @@
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//;Ensure that your assembly code complies with the Procedure Call Standard for the ARM Architecture (AAPCS).
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//;
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//;The AAPCS describes a contract between caller functions and callee functions. For example, for integer or pointer types, it specifies that:
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//;
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//; Registers R0-R3 pass argument values to the callee function, with subsequent arguments passed on the stack.
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//; Register R0 passes the result value back to the caller function.
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//; Caller functions must preserve R0-R3 and R12, because these registers are allowed to be corrupted by the callee function.
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//; Callee functions must preserve R4-R11 and LR, because these registers are not allowed to be corrupted by the callee function.
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//;
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//;For more information, see the Procedure Call Standard for the ARM Architecture (AAPCS).
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//;WARNING!!! logic instructions all affect flags despite the 's' postfix arm_none_eabi_gcc doesn't like 's' instructions
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//; but the 's' affect flag instructions are the only ones the M0 supports
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//; because of this, issue the following code isn't compatible with other cores.
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.equ BSSR, 0x18
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.equ BRR, 0x28
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.equ OTYPER, 0x04
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.equ IDR, 0x10
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.equ NO_RESP, 0xFF
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.equ ACK, 0x01
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.equ NAK, 0x00
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.equ HERR, 0x0E
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.equ PERR, 0x09
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.macro swim_lo
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strh swim_mask, [swim_base, #BRR]
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.endm
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.macro swim_hi
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strh swim_mask, [swim_base, #BSSR]
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.endm
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.macro swim_pp
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strh pushpull, [swim_base, #OTYPER]
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.endm
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.macro swim_od
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strh opendrain, [swim_base, #OTYPER]
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.endm
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.equ SWIM_RD, 0x01
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.equ SWIM_WR, 0x02
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.equ SWIM_HS_BIT, 4
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.equ SWIM_HS_MSK, 0x10
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.equ HS_DELAY, 4
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.equ LS_DELAY, 22
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.globl swim_xfr
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.p2align 2
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.type swim_xfr,%function
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//;r0 - r3 contain function args (excess on stack)
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//;swim_xfr( data_pb, spddir_len, swim_base, swim_mask);
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//;spddir_len = (SWIM_RD_LS<<16) | len;
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//; stream .req a1 this arg is moved to variable reg after stack push
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stream_arg .req a1
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rv .req r0
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len .req a2
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swim_base .req a3
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swim_mask .req a4
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swim_xfr: //;Function entry point.
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.fnstart
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//;need a few extra variable registers, but they need to be preserved
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pushpull .req v1
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opendrain .req v2
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stream .req v3
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speed .req v4
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//;high registers r8-r12 are very limited following instructions can utilize them
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//; ADD, CMP, LDR PC-rel, BX, BLX, MSR, MSR
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//; Docs list that MOV can only use R0-7, but testing and compilation proves otherwise
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//; Additionally, arm_none_eabi_gcc uses MOV R8, R8 as it's NOP!!
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rdwr .req v5
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push {pushpull, opendrain, stream, speed, lr}
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mov speed, rdwr //;preserve r8 high register can't pop/push
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push {speed}
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//; move stream arg out of r0, and into variable register so r0 is free
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mov stream, stream_arg
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//; len contains speed and direction data, must trim off and move
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//; into variable registers
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//;spddir_len = (SWIM_RD/WR_LS/HS<<16) | len;
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mov r0, len
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lsr r0, #16
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cmp r0, #SWIM_HS_MSK
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bpl high_speed
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mov speed, #LS_DELAY
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b speed_dir
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high_speed:
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mov speed, #HS_DELAY
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speed_dir:
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//;mask out speed bit and store in rdwr
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//;shift speed bit left past carry
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lsl r0, #(16-SWIM_HS_BIT + 16) //;16-BIT shifts bit to b16, 16 shifts to carry = 28
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lsr r0, #(16-SWIM_HS_BIT + 16) //;carry doesn't shift in
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mov rdwr, r0
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//; mask out upper bits of len
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mov r0, #0xFF
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and len, r0
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//; ~83nsec per unit of delay change
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//;mov speed, #22 //;22 = 2.75usec bit time delay variable
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//;mov speed, #4 //;4 = 1.25usec bit time delay variable
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//;mov speed, #22
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//; set pushpull and opendrain to values we can write to otyper register
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//; to quickly change direction of the SWIM pin only
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ldr pushpull, [swim_base, #OTYPER]
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mov opendrain, pushpull
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//; variables hold current OTYPER register value
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//; set bit for opendrain, clear for pushpull
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orr opendrain, swim_mask
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bic pushpull, swim_mask
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//; now these registers can be written directly to otyper GPIO reg
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//; to quickly change SWIM pin direction and not affect other pins
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//;set flags so first bit is header '0' "from host"
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//;the stream comes in as 16bit value with stream bit 7 in bit position 15
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//;shift the stream left so the current transfer bit is in bit position 31
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//;15 -> 30 is 15bit shifts, this leaves header zero in bit position 31
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//;store stream in r4
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lsl stream, #15
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bit_start:
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//;always start going low
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swim_lo
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//;current bit is stored in bit31 and Negative flag is set if
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//;current bit is '1'
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bpl cur_bit_zero
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//;delay to extend low time for '1'
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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//;go high since current bit is '1'
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swim_pp
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swim_hi
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swim_od
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b det_next_bit
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cur_bit_zero:
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//;must delay same amount of time as instructions above since branch
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//;add delay here to make '0' longer until equal to '1'
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mov r0, #1
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bl delay_r0
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det_next_bit:
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//;determine if this is the last bit
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sub len, #1
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//;if last bit, go to stream end to prepare for ACK/NAK latch
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bmi out_end
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//;delay until 'go high' time for '0'
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//;add delay here to make all bit transfers longer
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//;20-> 2.56usec bit time
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//;21-> 2.65usec
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//;22-> 2.73usec
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mov r0, speed ;//4-HS 22-LS
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bl delay_r0
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nop //;22+nop = 2.75usec = low speed timing perfect!
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//; high speed bit time has same 0-high, 1-lo time
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//; only difference is bit time is 1.25usec
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//;Negative flag is now set for '1', and clear for '0'
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//;always go high for '0' (no effect if already high for '1')
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swim_pp
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swim_hi
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swim_od
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//;delay to extend high time of '0'
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nop
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nop
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//;determine next bit value
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lsl stream, #1
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//;go to bit start
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b bit_start
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out_end:
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//;delay until 'go high' time for '0'
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mov r0, speed
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sub r0, #1 ;//this decrement keeps both HS and LS perfectly aligned
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bl delay_r0
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//;always go high for '0' (no effect if already high for '1')
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swim_pp
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swim_hi
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swim_od
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//;delay until time to latch ACK/NAK from device
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mov r0, #4 //;1-2:NR 3: usually RESP, not always/5-varies RESP/NO RESP
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//; sometime the device takes longer...
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//; 3 was failing for some, inc to 5
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//; 5 works, '1' NAK has low pulse width of 500-600nsec, trying 4
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//; 4 seems stable. low pulse time is 400-550nsec
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bl delay_r0
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//;first need to ensure device is actually responding
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//;sample when output should be low for a 1 or 0
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//;appears the device inserts a little delay ~220nsec between final host bit
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//;and ACK/NAK
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//;total time between host high (parity bit = '0')
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//;and device ACK/NAK low is ~450nsec
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//;debug toggle pushpull below
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//;measurements showed pulse ~100nsec after device took SWIM low with 3 above
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//;swim_pp
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//;swim_od
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//;latch SWIM pin value from GPIO IDR
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ldrh rv, [swim_base, #IDR]
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and rv, swim_mask
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//;if it wasn't low, then the device didn't respond, so return error designating that
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//;__asm volatile ("bne no_response\n\t");
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beq wait_ack_nak
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//;return 0xFF
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mov rv, #NO_RESP
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b exit_swim
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wait_ack_nak:
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//;don't have a strong enough pull-up resistor on SWIM pin
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//;to compensate for this we can cheat by quickly toggling
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//;to push-pull after device should have gone high for ACK = '0'
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//;this does create bus contension for breif period but don't have much choice here..
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//;only other alternative is to install pullup on board/programmer
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//;swim_pp no delay_r0 outputs pulse ~240nsec after device goes low with 3 above
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//;swim_od
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//; 3 above, and 2 here equates to pulse high 640nsec after device goes low
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//; 3 above, and 1 here equates to pulse high 460nsec after device goes low
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//; 3 above wasn't stable, incremented to 4 and works, give 400-550nsec pulse low
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//; mov r0, #1
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//; bl delay_r0
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;//r0=1: for ACK, artf pullup enabled 150-300nsec after device stops driving low
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;//this is okay timing allowance as being early would cause misread
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;//could possibly tighten with nops instead..
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nop
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nop
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nop
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nop //;4 nops = 250-350nsec low pulse width for ACK '1'
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nop
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nop //;5 nops = 300-450nsec low pulse width
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swim_pp
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swim_od
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//;now we can sample for NAK/ACK as artifical pullup has been inserted above
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//;if device output ACK, the artificial pullup doesn't cause contension
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//;but if device output NAK "0" device should still be driving low
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//;latch SWIM pin value from GPIO IDR
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ldrh rv, [swim_base, #IDR]
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and rv, swim_mask
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//; NAK: rv=0, ACK: rv=swim_mask
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beq return_nak
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mov rv, #ACK
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//; device sent ACK, if this is a read operation
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//; need to capture data sent by the device
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mov stream, #SWIM_WR
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cmp rdwr, stream
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beq exit_swim
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//; Sent the last byte of the command successfully
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//; Now read in data from device
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//; A bit of a challenge because of lacking legit pullup
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//; setup for read transfer
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mov len, #9 //;read 9bits total, then output ACK
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//; poll until device takes SWIM low for header bit
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//; perhaps setting an interrupt and waiting for it would be better
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//; due to less jitter from polling..
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poll_header:
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ldrh stream, [swim_base, #IDR]
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and stream, swim_mask
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bne poll_header
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//;device took SWIM low
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//;pulse for artifical pullup
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mov r0, #1 //;1: 350-450nsec equates to 100-200nsec delay ~okay
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bl delay_r0
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//;nop
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//;nop
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//;nop //; 3xnop = 250-300nsec low pulse for '1' header from device
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//;nop //; 4xnop = 250-350nsec
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//;nop //; 5xnop = 250-300 never seems to change!!!!
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//; the device seems to stall for a little bit due to the delayed pull-up
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//; the bit time for the header seems to extend to ~3usec
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//; but perhaps we can take advantage of this to better align with the device
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//; add delay between here and read_next_bit to lengthen header bit
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//; seemed to be a little early at times..
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swim_pp
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swim_od
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b read_next_bit
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.p2align 4
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read_next_bit:
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swim_pp
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swim_od
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//; header bit '1' is now high
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//; give a little delay between push pulse and reading
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//; this instruction can be performed out of order
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//; this didn't end up being a real problem, but it can't hurt
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lsl stream, #1
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//; read bit, should be '1' for header on first read
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//; sample and place value in carry, then rotate in
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ldrh r0, [swim_base, #IDR]
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and r0, swim_mask
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//; Z flag contains inverse of bit
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mrs r0, APSR
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//; bit 30 of r0 contains inverse of bit
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//; shift left to mask away any upper bits
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lsl r0, #1
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//; shift right to mask away lower bits
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lsr r0, #31
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//; shift stream and or in r0 (stream does have mask bit set from poll loop)
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//; moved up to provide delay between push and read
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//;lsl stream, #1
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orr stream, r0
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//; now stream holds the inverse stream (plus mask junk on upper half)
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//; wait bit time, enable artifical pullup, and sample
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mov r0, speed
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sub r0, #2 //; need to save some delay for after pushing '0' high
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bl delay_r0
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//; push high for logic '0'
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//;swim_pp
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//;swim_od
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//;mov r0, #2
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//;bl delay_r0
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//; above isn't always getting SWIM pin high for '0'
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//; can only assume that it's too early
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swim_pp
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swim_od
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mov r0, #2
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bl delay_r0
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//; seems to drop out at times..
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//; adding a check here to verify that SWIM is high looks like it would
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//; catch when the device drops out
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//; check if last bit in read
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sub len, #1
|
||||
//;if last bit, go to stream end to prepare for ACK/NAK latch
|
||||
bpl read_next_bit
|
||||
|
||||
//; last bit calc and send parity, or just always send ACK
|
||||
//; could send back to poll header but not sure it's worth retrying..
|
||||
//; not sure a failure would even allow us to properly send a NAK
|
||||
|
||||
always_send_ack:
|
||||
//; ACK is a '1' from host, so need a short pulse low
|
||||
//; this is actually a little late, but seems the device sends it a little late as well
|
||||
//; so this happens to align pretty well with the device's timing
|
||||
swim_lo
|
||||
swim_pp
|
||||
mov r0, #1
|
||||
bl delay_r0
|
||||
swim_hi
|
||||
swim_od
|
||||
|
||||
//; organize return data
|
||||
//; MSB NAK/NORESP from last write
|
||||
//; if ACK, then return read result
|
||||
//; TIMEOUT, HEADER error, PAIRITY error
|
||||
//; ACK entire transfer good!
|
||||
//; LSB data read back
|
||||
|
||||
//; stream data sturcture
|
||||
//; upper bits may contain swim_mask value
|
||||
//; all values inverted:
|
||||
//; b9 header '1' -> '0'
|
||||
//; b8-1 data inverted 1's compliment
|
||||
//; b0 pairity inverted
|
||||
|
||||
//; write corrupted data for testing
|
||||
//; inverted 1 header bit - F0 data - 0 pairitybit
|
||||
//; 0 0F 1
|
||||
//; mov stream, #0x1F ;// good data should report 0xF0 - ACK
|
||||
//; mov stream, #0x1E ;// toggle pairity data should report PAIRITY ERROR
|
||||
|
||||
;// bad header data
|
||||
//; mov stream, #0x80
|
||||
//; mov rv, #2
|
||||
//; lsl stream, rv
|
||||
//; mov rv, #1 ;// set correct pairity
|
||||
//; orr stream, rv
|
||||
|
||||
//; store result as-is
|
||||
mov rv, stream
|
||||
|
||||
//; check that header was read as '1' (from device) and stored as '0'
|
||||
mov len, #0x80 ;// bad header data would have bit 9 set ('1' device header is inverted)
|
||||
mov swim_mask, #2
|
||||
lsl len, swim_mask ;// shift bit 7 into bit 9
|
||||
and stream, len
|
||||
//; should be zero if header stored as '0'
|
||||
bne header_error
|
||||
|
||||
//; calc pairity
|
||||
//; must add to registers to add with carry
|
||||
//; swim_mask no longer needed
|
||||
mov swim_mask, #0
|
||||
//; store stream temporarily in len reg while shifting pairity bit to carry
|
||||
lsr len, rv, #1
|
||||
|
||||
//; stream should be zero on entry
|
||||
//; add inverted pairity bit
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
//; add bit0-3
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
//; add bit4-7
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
adc stream, swim_mask
|
||||
lsr len, #1
|
||||
adc stream, swim_mask
|
||||
|
||||
//; individual sumation of all bits should be even when pairity included
|
||||
//; but for inverted data, the sum should be odd
|
||||
//; shift sum lsbit into carry and verify it's set (equates to odd)
|
||||
lsr stream, #1
|
||||
bcc pairity_error
|
||||
|
||||
//; all is good, just return the inverted data!
|
||||
lsr rv, #1
|
||||
//; mask out data alone
|
||||
mov len, #0xFF
|
||||
and rv, len
|
||||
//; invert data to true data
|
||||
eor rv, len
|
||||
|
||||
//; shift to upper byte
|
||||
lsl rv, #8
|
||||
//; add in the ACK to lower byte
|
||||
add rv, #ACK
|
||||
//; since things are little endian
|
||||
//; the output is a 16bit int
|
||||
//; so the value we output will be byte swapped
|
||||
//; when interpreted as 16bit int
|
||||
|
||||
b exit_swim
|
||||
|
||||
header_error:
|
||||
//; header wasn't '1' as expected when reading from device
|
||||
mov rv, #HERR
|
||||
b exit_swim
|
||||
|
||||
pairity_error:
|
||||
mov rv, #PERR
|
||||
b exit_swim
|
||||
|
||||
return_nak:
|
||||
mov rv, #NAK
|
||||
|
||||
exit_swim:
|
||||
//;r0 contains return value on exit (already done prior to this point)
|
||||
//;r4-r11 & lr must be preserved to entry values
|
||||
pop {speed}
|
||||
mov rdwr, speed //;restore r8 high register can't pop/push
|
||||
pop {pushpull, opendrain, stream, speed, pc}
|
||||
|
||||
//; bx lr //;Return by branching to the address in the link register.
|
||||
.fnend
|
||||
|
||||
|
||||
//;.globl delay_r0
|
||||
//; ~83nsec per unit of delay change
|
||||
.p2align 2
|
||||
.type delay_r0,%function
|
||||
count .req a1
|
||||
delay_r0: //;Function entry point.
|
||||
.fnstart
|
||||
sub count, #1
|
||||
bne delay_r0
|
||||
bx lr
|
||||
.fnend
|
||||
|
|
@ -22,6 +22,7 @@ uint8_t swim_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *
|
|||
#define RD_LEN 0
|
||||
#define RD0 1
|
||||
#define RD1 2
|
||||
uint16_t *ret_hword = (uint16_t*) &rdata[1];
|
||||
|
||||
#define BYTE_LEN 1
|
||||
#define HWORD_LEN 2
|
||||
|
|
@ -33,10 +34,13 @@ uint8_t swim_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *
|
|||
rdata[RD0] = swim_out( 0x0000, 4); break;
|
||||
case WOTF:
|
||||
rdata[RD_LEN] = BYTE_LEN;
|
||||
rdata[RD0] = swim_woft(operand, miscdata); break;
|
||||
// case ROTF:
|
||||
// rdata[RD_LEN] = BYTE_LEN;
|
||||
// rdata[RD0] = swim_roft(); break;
|
||||
rdata[RD0] = swim_woft( operand, miscdata ); break;
|
||||
case ROTF:
|
||||
rdata[RD_LEN] = HWORD_LEN;
|
||||
//this assignment actually undoes the byte swap
|
||||
//first index of data includes NAK/ACK just like write routines which only return ACK/NAK
|
||||
//second index of data includes actual byte read back
|
||||
*ret_hword = swim_roft( operand ); break;
|
||||
default:
|
||||
//opcode doesn't exist
|
||||
return ERR_UNKN_SWIM_OPCODE;
|
||||
|
|
@ -325,10 +329,84 @@ uint16_t append_pairity(uint8_t n)
|
|||
}
|
||||
}
|
||||
|
||||
/* Desc:read byte from SWIM
|
||||
* Pre: swim must be activated
|
||||
* Post:
|
||||
* Rtn: should return success/error and value read
|
||||
*/
|
||||
|
||||
//must match swim.s .equ statements!!!
|
||||
#define SWIM_RD_LS 0x01
|
||||
#define SWIM_WR_LS 0x02
|
||||
#define SWIM_RD_HS 0x11
|
||||
#define SWIM_WR_HS 0x12
|
||||
|
||||
uint16_t swim_roft(uint16_t addr)
|
||||
{
|
||||
//If >24Mhz SYSCLK, must add wait state to flash
|
||||
//can also enable prefetch buffer
|
||||
FLASH->ACR = FLASH_ACR_PRFTBE | 0x0001;
|
||||
//switch to 48Mhz
|
||||
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL;
|
||||
|
||||
uint16_t data_pb;
|
||||
uint32_t ack_data;
|
||||
uint32_t spddir_len;
|
||||
//bit sequence:
|
||||
//1bit header "0" Host comm
|
||||
//3bit command b2-1-0 "001" ROTF
|
||||
//1bit pairity xor of cmd "1"
|
||||
//1bit ACK "1" or NAK "0" from device
|
||||
// 0b0_0011
|
||||
data_pb = 0x3000;
|
||||
spddir_len = (SWIM_WR_LS<<16) | 4; //data + pairity ( '0' header not included)
|
||||
ack_data = swim_xfr( data_pb, spddir_len, swim_base, swim_mask);
|
||||
if (ack_data != ACK) goto end_swim;
|
||||
|
||||
//write N "number of bytes for ROTF"
|
||||
data_pb = 0x0180;
|
||||
spddir_len = (SWIM_WR_LS<<16) | 9;
|
||||
ack_data = swim_xfr( data_pb, spddir_len, swim_base, swim_mask);
|
||||
if (ack_data != ACK) goto end_swim;
|
||||
|
||||
//write @E extended address of write
|
||||
//always 0x00 since targetting stm8s003 which only has one section
|
||||
data_pb = 0x0000;
|
||||
spddir_len = (SWIM_WR_LS<<16) | 9;
|
||||
ack_data = swim_xfr( data_pb, spddir_len, swim_base, swim_mask);
|
||||
if (ack_data != ACK) goto end_swim;
|
||||
|
||||
//write @H high address of write
|
||||
data_pb = append_pairity( addr>>8 );
|
||||
spddir_len = (SWIM_WR_LS<<16) | 9;
|
||||
ack_data = swim_xfr( data_pb, spddir_len, swim_base, swim_mask);
|
||||
if (ack_data != ACK) goto end_swim;
|
||||
|
||||
//write @L high address of write
|
||||
data_pb = append_pairity( addr );
|
||||
//this is a read xfr because device will output data immediately after
|
||||
//writting last byte of command info
|
||||
spddir_len = (SWIM_RD_LS<<16) | 9;
|
||||
ack_data = swim_xfr( data_pb, spddir_len, swim_base, swim_mask);
|
||||
|
||||
//read DATA portion of write
|
||||
|
||||
//More bytes can be written
|
||||
//any time NAK is recieved must resend byte
|
||||
end_swim:
|
||||
|
||||
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_HSE;
|
||||
//Don't need wait states or prefetch buffer anymore
|
||||
FLASH->ACR = 0x0000;
|
||||
return ack_data;
|
||||
|
||||
}
|
||||
|
||||
|
||||
/* Desc:write byte to SWIM
|
||||
* Pre: swim must be activated
|
||||
* Post:
|
||||
* Rtn: 0-NAK, 1-ACK beware, no response looks like ACK!
|
||||
* Rtn: 0-NAK, 1-ACK, 0xFF no response
|
||||
*/
|
||||
uint8_t swim_woft(uint16_t addr, uint8_t data)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -13,7 +13,11 @@ uint8_t swim_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *
|
|||
void swim_activate();
|
||||
void swim_reset();
|
||||
uint8_t swim_out(uint16_t stream, uint8_t len);
|
||||
uint16_t swim_roft(uint16_t addr);
|
||||
uint8_t swim_woft(uint16_t addr, uint8_t data);
|
||||
uint16_t append_pairity(uint8_t n);
|
||||
|
||||
//assembly functions from swim.s
|
||||
extern uint32_t swim_xfr( uint16_t data_pb, uint32_t spddir_len, GPIO_TypeDef *swim_base, uint16_t swim_mask);
|
||||
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -122,6 +122,8 @@ void init_clock()
|
|||
//at startup HSI is selected SW = 00
|
||||
RCC->CFGR |= RCC_CFGR_SW_HSE;
|
||||
|
||||
//TODO poll RCC->CFGR SWS bits to ensure sysclk switched over
|
||||
|
||||
//Now the SYSCLK is running directly off the HSE 16Mhz xtal
|
||||
|
||||
/* (1) Test if PLL is used as System clock */
|
||||
|
|
|
|||
|
|
@ -405,8 +405,13 @@ local function swim( opcode, operand, misc, data )
|
|||
end
|
||||
|
||||
--process the return data string and return it to calling function
|
||||
RETURN_ACK_IDX = 3
|
||||
RETURN_DAT_IDX = 4
|
||||
if data_len then
|
||||
return string_to_int( data:sub(RETURN_DATA, data_len+RETURN_DATA), data_len)
|
||||
--return string_to_int( data:sub(RETURN_DATA, data_len+RETURN_DATA), data_len)
|
||||
error_code = data:byte(RETURN_ACK_IDX)
|
||||
data_len = data:byte(RETURN_DAT_IDX)
|
||||
return error_code, data_len
|
||||
else
|
||||
return nil
|
||||
end
|
||||
|
|
|
|||
|
|
@ -38,11 +38,26 @@ function main ()
|
|||
dict.io("SWIM_INIT", "SWIM_ON_EXP0")
|
||||
dict.swim("SWIM_ACTIVATE")
|
||||
|
||||
--holds SWIM pin low for 16usec+ to reset SWIM comms incase of error
|
||||
dict.swim("SWIM_RESET")
|
||||
|
||||
|
||||
--write 0A0h to SWIM_CSR
|
||||
--bit 5: allows entire memory range to be read & swim reset to be accessed
|
||||
--bit 7: masks internal reset sources (like WDT..?)
|
||||
print("wotf SWIM_CSR:", dict.swim("WOTF", 0x7F80, 0xA0))
|
||||
|
||||
--read SWIM_CSR
|
||||
print("rotf SWIM_CSR:", string.format("%X %X", dict.swim("ROTF", 0x7F80)))
|
||||
print("rotf SWIM_CSR:", string.format("%X %X", dict.swim("ROTF", 0x7F80)))
|
||||
print("rotf SWIM_CSR:", string.format("%X %X", dict.swim("ROTF", 0x7F80)))
|
||||
print("rotf SWIM_CSR:", string.format("%X %X", dict.swim("ROTF", 0x7F80)))
|
||||
print("rotf SWIM_CSR:", string.format("%X %X", dict.swim("ROTF", 0x7F80)))
|
||||
dict.swim("SWIM_RESET")
|
||||
|
||||
print("wotf SRST:", dict.swim("SWIM_SRST"))
|
||||
print("wotf SWIM_CSR:", dict.swim("WOTF", 0x7F80, 0xA0))
|
||||
|
||||
--now the SRST command is available, whole memory range available, and internal resets disabled
|
||||
--by default there is now a breakpoint set at reset vector
|
||||
|
||||
|
|
|
|||
|
|
@ -28,7 +28,7 @@
|
|||
//SWIM commands
|
||||
#define SWIM_SRST 2 //reset device RL=3 (error, len, NAK/ACK)
|
||||
|
||||
#define ROTF 0x11 //read on the fly only one byte RL=3 (error, len, data)
|
||||
#define ROTF 0x11 //read on the fly only one byte RL=4 (usberror, len, swimerror, data)
|
||||
//#define ROTF_8B 0x18 //read on the fly RL=8
|
||||
//#define ROTF_128B 0x1F //read on the fly RL=128 (current max due to 254B limit)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue