new file: io.c
-creation of io file modified: main.c -moving io setup to io.c new file: pinport.h -creation of pinport file, intended to be avr specific code from macro.h
This commit is contained in:
paul eeepc
parent
b8be4b768a
commit
5620b34a9e
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#include <avr/io.h>
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#include "pinport.h"
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//Goal is to silience everything
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//Clear busses and pull up when able
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void io_init()
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{
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//pull up data bus
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DATA_IP();
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DATA_HI();
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//pull up addr[7:0] bus
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ADDR_IP();
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ADDR_HI();
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//EXP0 input no pullup
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//SNES /RESET pin disables SRAM on first few pcb versions
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//NES PRG-ROM /OE on old INL-ROM v1 boards w/pulldown
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//NED PRG-ROM /WE on INL-ROM v3 boards w/pullup
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//NES CPLD JTAG TDO non-5v tolerant
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EXP0_IP();
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EXP0_LO();
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//IRQ pullup NES boards will drive this pin
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IRQ_IP();
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IRQ_HI();
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//LED LAST displaying complete..
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}
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@ -124,10 +124,13 @@ int main()
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usbDeviceConnect();
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//intialize i/o to default state
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io_init();
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//configure LED PORT/DDR
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SETUP_LED();
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//SETUP_LED();
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//Always startup with LED ON
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LED_ON();
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//LED_ON();
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//enable interrupts
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sei();
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@ -0,0 +1,154 @@
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#include <avr/io.h>
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//#define NOP() do { __asm__ __volatile__ ("nop"); } while (0)
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// used for a very short delay
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#define LO 0x00
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#define HI 0xFF
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//#define TRUE 0x00
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//FALSE is ANYTHING but TRUE, the value signifies the error number
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//PIN DEFINITIONS
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//AUX PORTD
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#define EXP0 PD0 //RESET_n on SNES
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#define LED PD1
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#define EXP9 PD1 //dual purposed pin
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#define USBP PD2
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#define IRQ PD3
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#define USBM PD4
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#define CIA10 PD5
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#define BL PD6
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#define XOE PD7 //Only X_OE on purple and green boards
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//X_OE and X_CLK on yellow final boards
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//CTL PORTC
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#define M2 PC0
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#define PCE PC1 //SNES /ROMSEL
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#define PRW PC2
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#define AXL PC3 //Free on green and yellow boards
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//Also AXL /OE on Yellow boards
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#define CRD PC4 //SNES /RD
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#define CWR PC5 //SNES /WR
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#define CICE PC6
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#define AHL PC7 //Also AXL on green proto boards
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//PORT DEFINITIONS
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#define ADDR_OUT PORTA
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#define ADDR_IN PINA
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#define ADDR_DDR DDRA
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#define DATA_OUT PORTB
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#define DATA_IN PINB
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#define DATA_DDR DDRB
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//#define UP_ADDR PORTB
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//second revision moves this to PORTA and combines AXL/AHL
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//#define X_ADDR PORTB
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#define CTL_OUT PORTC
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#define CTL_IN PINC
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#define CTL_DDR DDRC
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#define AUX_OUT PORTD
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#define AUX_IN PIND
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#define AUX_DDR DDRD
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#define DATA_IP() DATA_DDR = LO
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#define DATA_OP() DATA_DDR = HI
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#define DATA_HI() DATA_OUT = HI
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#define DATA_LO() DATA_OUT = LO
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#define ADDR_IP() ADDR_DDR = LO
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#define ADDR_OP() ADDR_DDR = HI
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#define ADDR_HI() ADDR_OUT = HI
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#define ADDR_LO() ADDR_OUT = LO
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// //AHL, AXL, are always output and high, unless individually asserted.
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// #define CTL_IP() CTL_DDR = 0b10001000// &= ((1<<AHL) | (1<<AXL))
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// #define CTL_OP() CTL_DDR = 0b10111111 //&= ~(1<<CICE); CTL_DDR |= ~((1<<AHL) | (1<<AXL) | (1<<CICE)) //CIRAM /CE is always input
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// #define CTL_HI() CTL_OUT |= ~((1<<AHL) | (1<<AXL))
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// //maintain these high unless individually asserted
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// #define CTL_LO() CTL_OUT &= ((1<<AHL) | (1<<AXL))
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//
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// //LED and XOE are separately asserted due to always outputs
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// #define AUX_IP() AUX_DDR &= ((1<<USBP) | (1<<USBM) | (1<<LED) | (1<<XOE))
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// //#define AUX_OP() AUX_DDR |= ~((1<<USBP) | (1<<USBM) | (1<<LED) | (1<<XOE))
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// #define AUX_HI() AUX_OUT |= ~((1<<USBP) | (1<<USBM) | (1<<LED) | (1<<XOE))
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// #define AUX_LO() AUX_OUT &= ((1<<USBP) | (1<<USBM) | (1<<LED) | (1<<XOE))
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//
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// //SNES copy cart needs CIRAM A10 and CIRAM /CE to be outputs
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// #define CC_OP() AUX_DDR |= (1<<CIA10); CTL_DDR |= (1<<CICE)
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// #define CC_IP() AUX_DDR &= ~(1<<CIA10); CTL_DDR &= ~(1<<CICE)
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#define SETUP_LED() AUX_DDR |= (1<<LED)
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#define LED_ON() AUX_OUT |= (1<<LED)
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#define LED_OFF() AUX_OUT &= ~(1<<LED)
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#define SETUP_ADDR_X() AUX_DDR |= (1<<XOE)
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#define DISABLE_ADDR_X() AUX_OUT |= (1<<XOE)
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#define ENABLE_ADDR_X() AUX_OUT &= ~(1<<XOE)
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#define SETUP_AHL() CTL_DDR |= (1<<AHL); CTL_OUT |= (1<<AHL) //output high
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#define SETUP_AXL() CTL_DDR |= (1<<AXL); CTL_OUT |= (1<<AXL) //output high
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#define LATCH_AHL() CTL_OUT &= ~(1<<AHL); CTL_OUT |= (1<<AHL) //toggle low -> high
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#define LATCH_AXL() CTL_OUT &= ~(1<<AXL); CTL_OUT |= (1<<AXL) //toggle low -> high
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#define M2_IP() CTL_DDR &= ~(1<<M2)
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#define M2_OP() CTL_DDR |= (1<<M2)
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#define M2_HI() CTL_OUT |= (1<<M2)
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#define M2_LO() CTL_OUT &= ~(1<<M2)
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#define CYCLE() CTL_OUT |= (1<<M2); NOP(); NOP(); NOP(); CTL_OUT &= ~(1<<M2); NOP(); NOP(); NOP(); CTL_OUT |= (1<<PCE) //toggle M2 high -> low for CPU access cycle, and takes PRG /CE high if it was low
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#define PCE_HI() CTL_OUT |= (1<<PCE)
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#define PCE_LO() CTL_OUT &= ~(1<<PCE)
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#define CICE_HI() CTL_OUT |= (1<<CICE)
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#define CICE_LO() CTL_OUT &= ~(1<<CICE)
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#define PRG_RD() CTL_OUT |= (1<<PRW)
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#define PRG_WR() CTL_OUT &= ~(1<<PRW)
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// #define PRG_RD_PCE_HI() CTL_OUT |= (1<<PRW) | (1<<PCE)
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// #define PRG_WR_PCE_LO() CTL_OUT &= ~((1<<PRW) | (1<<PCE))
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//
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// //#define SNES_RD_SEL_HI() CTL_OUT |= (1<<CRD) | (1<<PCE)
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// #define SNES_WR_SEL_LO() CTL_OUT &= ~((1<<CWR) | (1<<PCE))
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// #define SNES_RD_SEL_LO() CTL_OUT &= ~((1<<CRD) | (1<<PCE))
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// #define SNES_CTL_HI() CTL_OUT |= (1<<CWR) | (1<<CRD) | (1<<PCE)
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// #define CC_CTL_HI() CTL_OUT |= (1<<PRW) | (1<<CICE); AUX_OUT |= (1<<CIA10)
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// //#define SNES_CTL_LO() CTL_OUT &= ~((1<<CWR) | (1<<CRD) | (1<<PCE))
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//
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// #define CHR_OEN() CTL_OUT |= (1<<CRD)
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// #define CHR_OE() CTL_OUT &= ~(1<<CRD)
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// #define CHR_WEN() CTL_OUT |= (1<<CWR) //Not-able (high)
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// #define CHR_WE() CTL_OUT &= ~(1<<CWR) //Enabled (low)
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//
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// #define CC_OEN() AUX_OUT |= (1<<CIA10)
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// #define CC_OE() AUX_OUT &= ~(1<<CIA10)
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// #define CC_WEN() CTL_OUT |= (1<<PRW) //Not-able (high)
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// #define CC_WE() CTL_OUT &= ~(1<<PRW) //Enabled (low)
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//
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// #define CHR_RD() CHR_WEN(); CHR_OE();
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// #define CHR_WR() CHR_OEN(); CHR_WE(); // /OE-hi /WE-lo
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//
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// // /WE-hi /OE-lo
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// // PRG RW hi, CIRAMA10 lo
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// #define CC_RD() CC_WEN(); CC_OE();
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// #define CC_WR() CC_OEN(); CC_WE();
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// //CIRAM A10 hi, PRGRW lo
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// // /OE-hi /WE-lo
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//EXP0 to only be pulled high because XO boards don't level shift EXP0
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//EXP0_LO(); replace with EXP0_LO(); EXP0_OP();
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//EXP0_HI(); replace with EXP0_IP(); EXP0_HI();
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#define EXP0_IP() AUX_DDR &= ~(1<<EXP0)
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#define EXP0_OP() AUX_DDR |= (1<<EXP0)
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#define EXP0_HIGH() AUX_OUT |= (1<<EXP0)
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#define EXP0_LOW() AUX_OUT &= ~(1<<EXP0)
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#define EXP0_HI() EXP0_IP(); EXP0_HIGH(); NOP(); NOP(); NOP(); NOP();
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#define EXP0_LO() EXP0_LOW(); EXP0_OP();
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#define PU_CICE() CTL_DDR &= ~(1<<CICE); CTL_OUT |= (1<<CICE);
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