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INL-retro-progdump
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Massively overdue commit of several months worth of random work. 

Mostly adding support for mappers as I needed it for my own hardware
builds:
-MMC1
-mapper 30
-easy NSF (still need to update for mapper verilog fix)
-action53 (still need to update for mapper verilog fix)
-dual port board flashing
-colordreams, not sure if I actually got this working
-color ninja, just a special CPLD version of colordreams for ninja boards

Just started working on SNES code.  slowly getting things up and working
outside of main inlretro.lua script similar to how NES has been handling
everything with it's own script.  Able to flash v3 boards fine.  v1 boards
flash without errors, but still having some mapping problems where it
verifies but won't boot.  v2 prototype flashes most bytes but not all,
seems v2 boards are much slower to output valid data..  But that may just
be the manufacturer ID codes..?

TODO next:
-bootloader dictionary that jumps to bootloader so don't have to manually
close jumper on the board.
-turn on the watchdog timer for stm32
-create some sort of host timeout so reset button on programmer isn't as
useful
-allow firmware programing algos to be uploaded and executed from SRAM for
faster code that also doesn't require specific firmware builds to support
new mapers.
-Finish JTAG to simplify programing NES & SNES CPLDs
-Sort out swim issue with stm8s001 CICs
-add SWIM support for avr
This commit is contained in:
Paul Black ASUS win7 2018-07-08 20:23:44 -05:00
parent 3488a64fe2
commit 9c57f1bdb3
35 changed files with 5314 additions and 2447 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

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@ -1,7 +1,7 @@
Archive member included to satisfy reference by file (symbol) Archive member included to satisfy reference by file (symbol)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o (__aeabi_unwind_cpp_pr0) C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o (__aeabi_unwind_cpp_pr0)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(libunwind.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(libunwind.o)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) (restore_core_regs) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) (restore_core_regs)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o)
@ -51,11 +51,11 @@ c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o) (_exit) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o) (_exit)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o (__gnu_thumb1_case_uqi) C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o (__gnu_thumb1_case_uqi)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_shi.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_shi.o)
C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o (__gnu_thumb1_case_shi) C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o (__gnu_thumb1_case_shi)
c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o) c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o)
C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o (__gnu_thumb1_case_uhi) C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o (__gnu_thumb1_case_uhi)
Allocating common symbols Allocating common symbols
Common symbol size file Common symbol size file
@ -107,20 +107,23 @@ Discarded input sections
.ARM.exidx 0x00000000 0x8 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o .ARM.exidx 0x00000000 0x8 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
.ARM.attributes .ARM.attributes
0x00000000 0x1b c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o 0x00000000 0x1b c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.text 0x00000000 0x0 source/buffer.o (symbol from plugin) .text 0x00000000 0x0 source/buffer.o (symbol from plugin)
.text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.rodata.oper_info .rodata.oper_info
0x00000000 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x00000000 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.text 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.text 0x00000000 0x0 source/dump.o (symbol from plugin) .text 0x00000000 0x0 source/dump.o (symbol from plugin)
.text 0x00000000 0x0 source/flash.o (symbol from plugin) .text 0x00000000 0x0 source/flash.o (symbol from plugin)
.text 0x00000000 0x0 source/io.o (symbol from plugin) .text 0x00000000 0x0 source/io.o (symbol from plugin)
@ -134,9 +137,9 @@ Discarded input sections
.text 0x00000000 0x0 source/usb.o (symbol from plugin) .text 0x00000000 0x0 source/usb.o (symbol from plugin)
.text 0x00000000 0x0 source_stm_only/stm_init.o (symbol from plugin) .text 0x00000000 0x0 source_stm_only/stm_init.o (symbol from plugin)
.text 0x00000000 0x0 source_stm_only/usbstm.o (symbol from plugin) .text 0x00000000 0x0 source_stm_only/usbstm.o (symbol from plugin)
.data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .data 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .bss 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.ARM.extab 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .ARM.extab 0x00000000 0x0 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.data 0x00000000 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) .data 0x00000000 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.bss 0x00000000 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) .bss 0x00000000 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.debug_frame 0x00000000 0x2c4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) .debug_frame 0x00000000 0x2c4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
@ -402,11 +405,12 @@ Linker script and memory map
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o LOAD C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
LOAD source/buffer.o LOAD source/buffer.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o LOAD C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o LOAD C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o LOAD C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
LOAD C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
LOAD source/dump.o LOAD source/dump.o
LOAD source/flash.o LOAD source/flash.o
LOAD source/io.o LOAD source/io.o
@ -420,7 +424,7 @@ LOAD source/swim.o
LOAD source/usb.o LOAD source/usb.o
LOAD source_stm_only/stm_init.o LOAD source_stm_only/stm_init.o
LOAD source_stm_only/usbstm.o LOAD source_stm_only/usbstm.o
LOAD C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o LOAD C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
START GROUP START GROUP
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a
@ -434,12 +438,12 @@ END GROUP
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtend.o
LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtn.o
.text 0x08000000 0x3c2c .text 0x08000000 0x462c
*(.isr_vector) *(.isr_vector)
.isr_vector 0x08000000 0xc0 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .isr_vector 0x08000000 0xc0 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
0x08000000 __isr_vector 0x08000000 __isr_vector
*(.text*) *(.text*)
.text 0x080000c0 0x40 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .text 0x080000c0 0x40 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
0x080000c0 Reset_Handler 0x080000c0 Reset_Handler
0x080000fc TSC_IRQHandler 0x080000fc TSC_IRQHandler
0x080000fc ADC1_COMP_IRQHandler 0x080000fc ADC1_COMP_IRQHandler
@ -479,147 +483,164 @@ LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eab
0x080000fc USART1_IRQHandler 0x080000fc USART1_IRQHandler
0x080000fc TIM1_BRK_UP_TRG_COM_IRQHandler 0x080000fc TIM1_BRK_UP_TRG_COM_IRQHandler
.text.USB_IRQHandler .text.USB_IRQHandler
0x08000100 0x1890 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x08000100 0x18bc C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x08000100 USB_IRQHandler 0x08000100 USB_IRQHandler
.text.append_pairity
0x08001990 0x1e C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
*fill* 0x080019ae 0x2
.text.snes_rom_wr
0x080019b0 0x50 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x080019b0 snes_rom_wr
.text.snes_rom_rd
0x08001a00 0x30 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001a00 snes_rom_rd
.text.nes_ppu_wr
0x08001a30 0x58 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001a30 nes_ppu_wr
.text.nes_ppu_rd
0x08001a88 0x38 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001a88 nes_ppu_rd
.text.nes_cpu_rd
0x08001ac0 0x40 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001ac0 nes_cpu_rd
.text.discrete_exp0_prgrom_wr
0x08001b00 0x60 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001b00 discrete_exp0_prgrom_wr
.text.pbje_scan .text.pbje_scan
0x08001b60 0x12c C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x080019bc 0x12c C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.text.pbje_state_change .text.pbje_state_change
0x08001c8c 0x98 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x08001ae8 0x98 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.text.get_next_buff .text.get_next_buff
0x08001d24 0x54 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x08001b80 0x54 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.text.control_xfr_in.lto_priv.26
0x08001d78 0xbc C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001d78 control_xfr_in.lto_priv.26
.text.HardFault_Handler
0x08001e34 0x2 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001e34 HardFault_Handler
*fill* 0x08001e36 0x2
.text.swim_wotf
0x08001e38 0xb4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001e38 swim_wotf
.text.swim_rotf
0x08001eec 0xac C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001eec swim_rotf
.text.delay_us
0x08001f98 0x16 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o
0x08001f98 delay_us
*fill* 0x08001fae 0x2
.text.jtag_init_pbje .text.jtag_init_pbje
0x08001fb0 0xe0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x08001bd4 0xe0 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
0x08001fb0 jtag_init_pbje 0x08001bd4 jtag_init_pbje
.text.jtag_run_pbje.part.0 .text.jtag_run_pbje.part.0
0x08002090 0xd8 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x08001cb4 0xd8 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
0x08002090 jtag_run_pbje.part.0 0x08001cb4 jtag_run_pbje.part.0
.text.io_reset .text.io_reset
0x08002168 0x148 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x08001d8c 0x148 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
0x08002168 io_reset 0x08001d8c io_reset
.text.startup.main .text.startup.main
0x080022b0 0x63c C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x08001ed4 0xe14 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
0x080022b0 main 0x08001ed4 main
.text.append_pairity
0x08002ce8 0x1e C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
*fill* 0x08002d06 0x2
.text.nes_cpu_wr
0x08002d08 0x6c C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002d08 nes_cpu_wr
.text.nes_cpu_rd
0x08002d74 0x40 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002d74 nes_cpu_rd
.text.discrete_exp0_prgrom_wr
0x08002db4 0x58 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002db4 discrete_exp0_prgrom_wr
.text.control_xfr_in.lto_priv.33
0x08002e0c 0xbc C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002e0c control_xfr_in.lto_priv.33
.text.HardFault_Handler
0x08002ec8 0x2 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002ec8 HardFault_Handler
*fill* 0x08002eca 0x2
.text.swim_wotf
0x08002ecc 0xb4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002ecc swim_wotf
.text.swim_rotf
0x08002f80 0xac C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08002f80 swim_rotf
.text.delay_us
0x0800302c 0x16 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x0800302c delay_us
*fill* 0x08003042 0x2
.text.snes_rom_wr
0x08003044 0x4c C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08003044 snes_rom_wr
.text.snes_rom_rd
0x08003090 0x40 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08003090 snes_rom_rd
.text.mmc1_wr 0x080030d0 0x38 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x080030d0 mmc1_wr
.text.nes_dualport_wr
0x08003108 0x50 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08003108 nes_dualport_wr
.text.nes_dualport_rd
0x08003158 0x38 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08003158 nes_dualport_rd
.text.nes_ppu_wr
0x08003190 0x50 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x08003190 nes_ppu_wr
.text.nes_ppu_rd
0x080031e0 0x38 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
0x080031e0 nes_ppu_rd
.text.write_page.constprop.23
0x08003218 0x68 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
0x08003218 write_page.constprop.23
.text.nes_cpu_page_rd_poll.constprop.17 .text.nes_cpu_page_rd_poll.constprop.17
0x080028ec 0x68 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o 0x08003280 0x6c C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
0x080028ec nes_cpu_page_rd_poll.constprop.17 0x08003280 nes_cpu_page_rd_poll.constprop.17
*fill* 0x08002954 0xc .text.nes_ppu_page_rd_poll.constprop.16
.text 0x08002960 0x154 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o 0x080032ec 0x68 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
0x08002960 swim_xfr 0x080032ec nes_ppu_page_rd_poll.constprop.16
.text 0x08002ab4 0xa38 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) *fill* 0x08003354 0xc
0x08002d84 _Unwind_GetCFA .text 0x08003360 0x154 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
0x08002d88 __gnu_Unwind_RaiseException 0x08003360 swim_xfr
0x08002ddc __gnu_Unwind_ForcedUnwind .text 0x080034b4 0xa38 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
0x08002df0 __gnu_Unwind_Resume 0x08003784 _Unwind_GetCFA
0x08002e38 __gnu_Unwind_Resume_or_Rethrow 0x08003788 __gnu_Unwind_RaiseException
0x08002e54 _Unwind_Complete 0x080037dc __gnu_Unwind_ForcedUnwind
0x08002e58 _Unwind_DeleteException 0x080037f0 __gnu_Unwind_Resume
0x08002e68 _Unwind_VRS_Get 0x08003838 __gnu_Unwind_Resume_or_Rethrow
0x08002eb4 _Unwind_VRS_Set 0x08003854 _Unwind_Complete
0x08002f00 __gnu_Unwind_Backtrace 0x08003858 _Unwind_DeleteException
0x08003260 __aeabi_unwind_cpp_pr0 0x08003868 _Unwind_VRS_Get
0x0800326c __aeabi_unwind_cpp_pr1 0x080038b4 _Unwind_VRS_Set
0x08003278 __aeabi_unwind_cpp_pr2 0x08003900 __gnu_Unwind_Backtrace
0x08003284 _Unwind_VRS_Pop 0x08003c60 __aeabi_unwind_cpp_pr0
.text 0x080034ec 0x144 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(libunwind.o) 0x08003c6c __aeabi_unwind_cpp_pr1
0x080034ec __restore_core_regs 0x08003c78 __aeabi_unwind_cpp_pr2
0x080034ec restore_core_regs 0x08003c84 _Unwind_VRS_Pop
0x08003518 __gnu_Unwind_Restore_VFP .text 0x08003eec 0x144 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(libunwind.o)
0x0800351c __gnu_Unwind_Save_VFP 0x08003eec __restore_core_regs
0x08003520 __gnu_Unwind_Restore_VFP_D 0x08003eec restore_core_regs
0x08003524 __gnu_Unwind_Save_VFP_D 0x08003f18 __gnu_Unwind_Restore_VFP
0x08003528 __gnu_Unwind_Restore_VFP_D_16_to_31 0x08003f1c __gnu_Unwind_Save_VFP
0x0800352c __gnu_Unwind_Save_VFP_D_16_to_31 0x08003f20 __gnu_Unwind_Restore_VFP_D
0x08003530 __gnu_Unwind_Restore_WMMXD 0x08003f24 __gnu_Unwind_Save_VFP_D
0x08003534 __gnu_Unwind_Save_WMMXD 0x08003f28 __gnu_Unwind_Restore_VFP_D_16_to_31
0x08003538 __gnu_Unwind_Restore_WMMXC 0x08003f2c __gnu_Unwind_Save_VFP_D_16_to_31
0x0800353c __gnu_Unwind_Save_WMMXC 0x08003f30 __gnu_Unwind_Restore_WMMXD
0x08003540 ___Unwind_RaiseException 0x08003f34 __gnu_Unwind_Save_WMMXD
0x08003540 _Unwind_RaiseException 0x08003f38 __gnu_Unwind_Restore_WMMXC
0x08003570 _Unwind_Resume 0x08003f3c __gnu_Unwind_Save_WMMXC
0x08003570 ___Unwind_Resume 0x08003f40 ___Unwind_RaiseException
0x080035a0 _Unwind_Resume_or_Rethrow 0x08003f40 _Unwind_RaiseException
0x080035a0 ___Unwind_Resume_or_Rethrow 0x08003f70 _Unwind_Resume
0x080035d0 _Unwind_ForcedUnwind 0x08003f70 ___Unwind_Resume
0x080035d0 ___Unwind_ForcedUnwind 0x08003fa0 _Unwind_Resume_or_Rethrow
0x08003600 ___Unwind_Backtrace 0x08003fa0 ___Unwind_Resume_or_Rethrow
0x08003600 _Unwind_Backtrace 0x08003fd0 _Unwind_ForcedUnwind
.text 0x08003630 0x3a8 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o) 0x08003fd0 ___Unwind_ForcedUnwind
0x08003684 __gnu_unwind_execute 0x08004000 ___Unwind_Backtrace
0x08003980 __gnu_unwind_frame 0x08004000 _Unwind_Backtrace
0x080039a8 _Unwind_GetRegionStart .text 0x08004030 0x3a8 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x080039b4 _Unwind_GetLanguageSpecificData 0x08004084 __gnu_unwind_execute
0x080039c8 _Unwind_GetTextRelBase 0x08004380 __gnu_unwind_frame
0x080039d0 _Unwind_GetDataRelBase 0x080043a8 _Unwind_GetRegionStart
.text.abort 0x080039d8 0x10 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o) 0x080043b4 _Unwind_GetLanguageSpecificData
0x080039d8 abort 0x080043c8 _Unwind_GetTextRelBase
.text.memcpy 0x080039e8 0x84 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-memcpy-stub.o) 0x080043d0 _Unwind_GetDataRelBase
0x080039e8 memcpy .text.abort 0x080043d8 0x10 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o)
0x080043d8 abort
.text.memcpy 0x080043e8 0x84 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-memcpy-stub.o)
0x080043e8 memcpy
.text._raise_r .text._raise_r
0x08003a6c 0x5c c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o) 0x0800446c 0x5c c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o)
0x08003a6c _raise_r 0x0800446c _raise_r
.text.raise 0x08003ac8 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o) .text.raise 0x080044c8 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o)
0x08003ac8 raise 0x080044c8 raise
.text._kill_r 0x08003adc 0x28 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o) .text._kill_r 0x080044dc 0x28 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o)
0x08003adc _kill_r 0x080044dc _kill_r
.text._getpid_r .text._getpid_r
0x08003b04 0x8 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o) 0x08004504 0x8 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o)
0x08003b04 _getpid_r 0x08004504 _getpid_r
.text._getpid 0x08003b0c 0x10 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o) .text._getpid 0x0800450c 0x10 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o)
0x08003b0c _getpid 0x0800450c _getpid
.text._kill 0x08003b1c 0x10 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(kill.o) .text._kill 0x0800451c 0x10 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(kill.o)
0x08003b1c _kill 0x0800451c _kill
.text._exit 0x08003b2c 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o) .text._exit 0x0800452c 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
0x08003b2c _exit 0x0800452c _exit
.text 0x08003b30 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o) .text 0x08004530 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
0x08003b30 __gnu_thumb1_case_uqi 0x08004530 __gnu_thumb1_case_uqi
.text 0x08003b44 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_shi.o) .text 0x08004544 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_shi.o)
0x08003b44 __gnu_thumb1_case_shi 0x08004544 __gnu_thumb1_case_shi
.text 0x08003b58 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o) .text 0x08004558 0x14 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o)
0x08003b58 __gnu_thumb1_case_uhi 0x08004558 __gnu_thumb1_case_uhi
*(.init) *(.init)
.init 0x08003b6c 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o .init 0x0800456c 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
0x08003b6c _init 0x0800456c _init
*(.fini) *(.fini)
.fini 0x08003b70 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o .fini 0x08004570 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
0x08003b70 _fini 0x08004570 _fini
*crtbegin.o(.ctors) *crtbegin.o(.ctors)
*crtbegin?.o(.ctors) *crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors) *(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
@ -632,53 +653,53 @@ LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eab
*(.dtors) *(.dtors)
*(.rodata*) *(.rodata*)
.rodata.config_desc .rodata.config_desc
0x08003b74 0x12 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x08004574 0x12 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.rodata.device_desc .rodata.device_desc
0x08003b86 0x12 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x08004586 0x12 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.rodata.string0_desc .rodata.string0_desc
0x08003b98 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x08004598 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.rodata.string1_desc .rodata.string1_desc
0x08003b9c 0x54 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x0800459c 0x54 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.rodata.string2_desc .rodata.string2_desc
0x08003bf0 0x3c C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x080045f0 0x3c C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
*(.eh_frame*) *(.eh_frame*)
.glue_7 0x08003c2c 0x0 .glue_7 0x0800462c 0x0
.glue_7 0x08003c2c 0x0 linker stubs .glue_7 0x0800462c 0x0 linker stubs
.glue_7t 0x08003c2c 0x0 .glue_7t 0x0800462c 0x0
.glue_7t 0x08003c2c 0x0 linker stubs .glue_7t 0x0800462c 0x0 linker stubs
.vfp11_veneer 0x08003c2c 0x0 .vfp11_veneer 0x0800462c 0x0
.vfp11_veneer 0x08003c2c 0x0 linker stubs .vfp11_veneer 0x0800462c 0x0 linker stubs
.v4_bx 0x08003c2c 0x0 .v4_bx 0x0800462c 0x0
.v4_bx 0x08003c2c 0x0 linker stubs .v4_bx 0x0800462c 0x0 linker stubs
.iplt 0x08003c2c 0x0 .iplt 0x0800462c 0x0
.iplt 0x08003c2c 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o .iplt 0x0800462c 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
.ARM.extab 0x08003c2c 0x30 .ARM.extab 0x0800462c 0x30
*(.ARM.extab* .gnu.linkonce.armextab.*) *(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab 0x08003c2c 0x24 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) .ARM.extab 0x0800462c 0x24 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.ARM.extab 0x08003c50 0xc c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o) .ARM.extab 0x08004650 0xc c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x08003c5c __exidx_start = . 0x0800465c __exidx_start = .
.ARM.exidx 0x08003c5c 0xd0 .ARM.exidx 0x0800465c 0xd0
*(.ARM.exidx* .gnu.linkonce.armexidx.*) *(.ARM.exidx* .gnu.linkonce.armexidx.*)
.ARM.exidx 0x08003c5c 0x8 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .ARM.exidx 0x0800465c 0x8 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
0x10 (size before relaxing) 0x10 (size before relaxing)
.ARM.exidx 0x08003c64 0x98 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) .ARM.exidx 0x08004664 0x98 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
0xd8 (size before relaxing) 0xd8 (size before relaxing)
.ARM.exidx 0x08003cfc 0x30 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o) .ARM.exidx 0x080046fc 0x30 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x48 (size before relaxing) 0x48 (size before relaxing)
0x08003d2c __exidx_end = . 0x0800472c __exidx_end = .
0x08003d2c __etext = ALIGN (0x4) 0x0800472c __etext = ALIGN (0x4)
.rel.dyn 0x08003d2c 0x0 .rel.dyn 0x0800472c 0x0
.rel.iplt 0x08003d2c 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o .rel.iplt 0x0800472c 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
.data 0x20000000 0x430 load address 0x08003d2c .data 0x20000000 0x430 load address 0x0800472c
0x20000000 __data_start__ = . 0x20000000 __data_start__ = .
*(vtable) *(vtable)
*(.data*) *(.data*)
@ -706,98 +727,98 @@ LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eab
0x20000430 . = ALIGN (0x4) 0x20000430 . = ALIGN (0x4)
0x20000430 __data_end__ = . 0x20000430 __data_end__ = .
.igot.plt 0x20000430 0x0 load address 0x0800415c .igot.plt 0x20000430 0x0 load address 0x08004b5c
.igot.plt 0x20000430 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o .igot.plt 0x20000430 0x0 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crtbegin.o
.bss 0x20000430 0x2fc load address 0x0800415c .bss 0x20000430 0x2fc load address 0x08004b5c
0x20000430 . = ALIGN (0x4) 0x20000430 . = ALIGN (0x4)
0x20000430 __bss_start__ = . 0x20000430 __bss_start__ = .
*(.bss*) *(.bss*)
.bss.buff0 0x20000430 0x14 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.buff0 0x20000430 0x14 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000430 buff0 0x20000430 buff0
.bss.buff1 0x20000444 0x14 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.buff1 0x20000444 0x14 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000444 buff1 0x20000444 buff1
.bss.buff2 0x20000458 0x14 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.buff2 0x20000458 0x14 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000458 buff2 0x20000458 buff2
.bss.buff3 0x2000046c 0x14 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.buff3 0x2000046c 0x14 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x2000046c buff3 0x2000046c buff3
.bss.cur_buff 0x20000480 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.cur_buff 0x20000480 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000480 cur_buff 0x20000480 cur_buff
.bss.cur_usb_load_buff .bss.cur_usb_load_buff
0x20000484 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000484 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss.incoming_bytes_remain .bss.incoming_bytes_remain
0x20000488 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000488 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
*fill* 0x20000489 0x3 *fill* 0x20000489 0x3
.bss.log 0x2000048c 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.log 0x2000048c 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss.new_address .bss.new_address
0x20000490 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000490 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
*fill* 0x20000491 0x1 *fill* 0x20000491 0x1
.bss.num_bytes_req.lto_priv.29 .bss.num_bytes_req.lto_priv.36
0x20000492 0x2 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000492 0x2 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000492 num_bytes_req.lto_priv.29 0x20000492 num_bytes_req.lto_priv.36
.bss.num_bytes_sending.lto_priv.28 .bss.num_bytes_sending.lto_priv.35
0x20000494 0x2 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000494 0x2 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000494 num_bytes_sending.lto_priv.28 0x20000494 num_bytes_sending.lto_priv.35
.bss.num_bytes_xfrd.lto_priv.27 .bss.num_bytes_xfrd.lto_priv.34
0x20000496 0x2 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000496 0x2 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000496 num_bytes_xfrd.lto_priv.27 0x20000496 num_bytes_xfrd.lto_priv.34
.bss.oper_info_struct .bss.oper_info_struct
0x20000498 0x20 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000498 0x20 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000498 oper_info_struct 0x20000498 oper_info_struct
.bss.pbje_command .bss.pbje_command
0x200004b8 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200004b8 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x200004b8 pbje_command 0x200004b8 pbje_command
.bss.pbje_data .bss.pbje_data
0x200004b9 0x20 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200004b9 0x20 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x200004b9 pbje_data 0x200004b9 pbje_data
.bss.pbje_numclk .bss.pbje_numclk
0x200004d9 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200004d9 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x200004d9 pbje_numclk 0x200004d9 pbje_numclk
.bss.pbje_status .bss.pbje_status
0x200004da 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200004da 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x200004da pbje_status 0x200004da pbje_status
.bss.raw_bank_status .bss.raw_bank_status
0x200004db 0x10 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200004db 0x10 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
*fill* 0x200004eb 0x1 *fill* 0x200004eb 0x1
.bss.raw_buffer16 .bss.raw_buffer16
0x200004ec 0x200 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200004ec 0x200 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss.req_dir 0x200006ec 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.req_dir 0x200006ec 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss.reqdir 0x200006ed 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.reqdir 0x200006ed 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss.reqtype 0x200006ee 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.reqtype 0x200006ee 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
*fill* 0x200006ef 0x1 *fill* 0x200006ef 0x1
.bss.rv16.4865 .bss.rv16.4882
0x200006f0 0x8 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200006f0 0x8 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.bss.swim_base .bss.swim_base
0x200006f8 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x200006f8 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x200006f8 swim_base 0x200006f8 swim_base
.bss.swim_pin 0x200006fc 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.swim_pin 0x200006fc 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x200006fc swim_pin 0x200006fc swim_pin
*fill* 0x200006fd 0x3 *fill* 0x200006fd 0x3
.bss.tck_base 0x20000700 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tck_base 0x20000700 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000700 tck_base 0x20000700 tck_base
.bss.tck_pin 0x20000704 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tck_pin 0x20000704 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000704 tck_pin 0x20000704 tck_pin
*fill* 0x20000705 0x3 *fill* 0x20000705 0x3
.bss.tdi_base 0x20000708 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tdi_base 0x20000708 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000708 tdi_base 0x20000708 tdi_base
.bss.tdi_pin 0x2000070c 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tdi_pin 0x2000070c 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x2000070c tdi_pin 0x2000070c tdi_pin
*fill* 0x2000070d 0x3 *fill* 0x2000070d 0x3
.bss.tdo_base 0x20000710 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tdo_base 0x20000710 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000710 tdo_base 0x20000710 tdo_base
.bss.tdo_pin 0x20000714 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tdo_pin 0x20000714 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000714 tdo_pin 0x20000714 tdo_pin
*fill* 0x20000715 0x3 *fill* 0x20000715 0x3
.bss.tms_base 0x20000718 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tms_base 0x20000718 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000718 tms_base 0x20000718 tms_base
.bss.tms_pin 0x2000071c 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .bss.tms_pin 0x2000071c 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x2000071c tms_pin 0x2000071c tms_pin
*fill* 0x2000071d 0x3 *fill* 0x2000071d 0x3
.bss.usbMsgPtr .bss.usbMsgPtr
0x20000720 0x4 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x20000720 0x4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x20000720 usbMsgPtr 0x20000720 usbMsgPtr
.bss.num_buff.4945 .bss.num_buff.4962
0x20000724 0x1 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x20000724 0x1 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
*(COMMON) *(COMMON)
*fill* 0x20000725 0x3 *fill* 0x20000725 0x3
COMMON 0x20000728 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-reent.o) COMMON 0x20000728 0x4 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-reent.o)
@ -809,12 +830,12 @@ LOAD c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eab
0x20000730 __end__ = . 0x20000730 __end__ = .
0x20000730 PROVIDE (end, .) 0x20000730 PROVIDE (end, .)
*(.heap*) *(.heap*)
.heap 0x20000730 0x0 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .heap 0x20000730 0x0 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
0x20000730 __HeapLimit = . 0x20000730 __HeapLimit = .
.stack_dummy 0x20000730 0xc00 .stack_dummy 0x20000730 0xc00
*(.stack*) *(.stack*)
.stack 0x20000730 0xc00 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .stack 0x20000730 0xc00 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
0x20001800 __StackTop = (ORIGIN (RAM) + LENGTH (RAM)) 0x20001800 __StackTop = (ORIGIN (RAM) + LENGTH (RAM))
0x20000c00 __StackLimit = (__StackTop - SIZEOF (.stack_dummy)) 0x20000c00 __StackLimit = (__StackTop - SIZEOF (.stack_dummy))
0x20001800 PROVIDE (__stack, __StackTop) 0x20001800 PROVIDE (__stack, __StackTop)
@ -826,83 +847,96 @@ OUTPUT(build_stm/inlretro_stm.elf elf32-littlearm)
.ARM.attributes .ARM.attributes
0x00000000 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o 0x00000000 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m/crti.o
.ARM.attributes .ARM.attributes
0x0000001e 0x1b C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o 0x0000001e 0x1b C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.ARM.attributes .ARM.attributes
0x00000039 0x2f C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o 0x00000039 0x2f C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.ARM.attributes .ARM.attributes
0x00000068 0x2f C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o 0x00000068 0x2f C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.ARM.attributes .ARM.attributes
0x00000097 0x2f C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o 0x00000097 0x2f C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.ARM.attributes .ARM.attributes
0x000000c6 0x21 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o 0x000000c6 0x2f C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.ARM.attributes .ARM.attributes
0x000000e7 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o) 0x000000f5 0x21 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.ARM.attributes .ARM.attributes
0x00000105 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_shi.o) 0x00000116 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
.ARM.attributes .ARM.attributes
0x00000123 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o) 0x00000134 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_shi.o)
.ARM.attributes
0x00000152 0x1e c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o)
.comment 0x00000000 0x7f .comment 0x00000000 0x7f
.comment 0x00000000 0x7f C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .comment 0x00000000 0x7f C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
0x80 (size before relaxing) 0x80 (size before relaxing)
.comment 0x0000007f 0x80 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .comment 0x0000007f 0x80 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.comment 0x0000007f 0x80 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .comment 0x0000007f 0x80 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.comment 0x0000007f 0x80 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.debug_line 0x00000000 0x148a .debug_line 0x00000000 0x18dc
.debug_line 0x00000000 0x6f C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .debug_line 0x00000000 0x6f C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.debug_line 0x0000006f 0xa01 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .debug_line 0x0000006f 0xa19 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.debug_line 0x00000a70 0x805 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .debug_line 0x00000a88 0x815 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.debug_line 0x00001275 0x122 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .debug_line 0x0000129d 0x3a8 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.debug_line 0x00001397 0xf3 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .debug_line 0x00001645 0x1a4 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.debug_line 0x000017e9 0xf3 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.debug_info 0x00000000 0x276d .debug_info 0x00000000 0x38f0
.debug_info 0x00000000 0x82 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .debug_info 0x00000000 0x82 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.debug_info 0x00000082 0x151d C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .debug_info 0x00000082 0x14d6 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.debug_info 0x0000159f 0x105d C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .debug_info 0x00001558 0x18c6 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.debug_info 0x000025fc 0xf6 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .debug_info 0x00002e1e 0x632 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.debug_info 0x000026f2 0x7b C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .debug_info 0x00003450 0x425 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.debug_info 0x00003875 0x7b C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.debug_abbrev 0x00000000 0x8e0 .debug_abbrev 0x00000000 0xa81
.debug_abbrev 0x00000000 0x14 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o .debug_abbrev 0x00000000 0x14 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.debug_abbrev 0x00000014 0x387 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans0.ltrans.o .debug_abbrev 0x00000014 0x387 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans0.ltrans.o
.debug_abbrev 0x0000039b 0x495 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .debug_abbrev 0x0000039b 0x396 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
.debug_abbrev 0x00000830 0x9c C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans2.ltrans.o .debug_abbrev 0x00000731 0x1ba C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans2.ltrans.o
.debug_abbrev 0x000008cc 0x14 C:\Users\Paul\AppData\Local\Temp\cc4F3l7j.o .debug_abbrev 0x000008eb 0x182 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans3.ltrans.o
.debug_abbrev 0x00000a6d 0x14 C:\Users\Paul\AppData\Local\Temp\cclhBf2A.o
.debug_aranges 0x00000000 0x130 .debug_aranges 0x00000000 0x178
.debug_aranges .debug_aranges
0x00000000 0x20 C:\Users\Paul\AppData\Local\Temp\ccYvVw2e.o 0x00000000 0x20 C:\Users\Paul\AppData\Local\Temp\cceBaBiJ.o
.debug_aranges .debug_aranges
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0x553 (size before relaxing) 0x4d9 (size before relaxing)
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.debug_frame 0x00000030 0x1d0 C:\Users\Paul\AppData\Local\Temp\ccmd3DOk.ltrans1.ltrans.o .debug_frame 0x00000030 0xd8 C:\Users\Paul\AppData\Local\Temp\ccHx4fn8.ltrans1.ltrans.o
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.stabstr 0x00000000 0x76 .stabstr 0x00000000 0x76
.stabstr 0x00000000 0x76 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o) .stabstr 0x00000000 0x76 c:/arm/gcc-arm-none-eabi-6-2017-q2-update-win32/bin/../lib/gcc/arm-none-eabi/6.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o)

95
firmware/source/dump.c
View File

@ -19,6 +19,16 @@ uint8_t dump_buff( buffer *buff ) {
switch ( buff->mem_type ) { switch ( buff->mem_type ) {
case PRGROM: case PRGROM:
addrH |= 0x80; //$8000 addrH |= 0x80; //$8000
if (buff->mapper == MMC1) {
//write bank value to bank table
//page_num shift by 6 bits A15 >> A9(1)
bank = (buff->page_num)>>6;
bank &= 0x0F; //only 4 bits in PRG
//LSb doesn't matter in 32KB mode
mmc1_wr(0x8000, 0x10, 1); //write bank to PRG-ROM bank register
mmc1_wr(0xE000, bank, 0); //write bank to PRG-ROM bank register
//TODO SXROM/SUROM require writting PRG-ROM MSb of address to CHR registers
}
if (buff->mapper == UxROM) { if (buff->mapper == UxROM) {
//addrH &= 0b1011 1111 A14 must always be low //addrH &= 0b1011 1111 A14 must always be low
addrH &= 0xBF; addrH &= 0xBF;
@ -26,8 +36,29 @@ uint8_t dump_buff( buffer *buff ) {
//page_num shift by 6 bits A14 >> A8(0) //page_num shift by 6 bits A14 >> A8(0)
bank = (buff->page_num)>>6; bank = (buff->page_num)>>6;
//Nomolos bank table @ CC84 //Nomolos bank table @ CC84
nes_cpu_wr( (0xCC84+bank), bank ); //nes_cpu_wr( (0xCC84+bank), bank );
//nes_cpu_wr( (0xE473+bank), bank ); //Owlia bank table @ CC84
nes_cpu_wr( (0xE473+bank), bank );
//Rushnattack
//nes_cpu_wr( (0x8000+bank), bank );
//twindragons
//nes_cpu_wr( (0xC000+bank), bank );
//h1
//nes_cpu_wr( (0xFFC0+bank), bank );
buff->cur_byte = nes_cpu_page_rd_poll( buff->data, addrH, buff->id,
//id contains MSb of page when <256B buffer
buff->last_idx, ~FALSE );
break;
}
if (buff->mapper == MAP30) {
//addrH &= 0b1011 1111 A14 must always be low
addrH &= 0xBF;
//write bank value to bank table
//page_num shift by 6 bits A14 >> A8(0)
bank = (buff->page_num)>>6;
//mapper register $C000-FFFF
nes_cpu_wr( 0xC000, bank );
buff->cur_byte = nes_cpu_page_rd_poll( buff->data, addrH, buff->id, buff->cur_byte = nes_cpu_page_rd_poll( buff->data, addrH, buff->id,
//id contains MSb of page when <256B buffer //id contains MSb of page when <256B buffer
@ -39,9 +70,9 @@ uint8_t dump_buff( buffer *buff ) {
//page_num shift by 7 bits A15 >> A8(0) //page_num shift by 7 bits A15 >> A8(0)
bank = (buff->page_num)>>7; bank = (buff->page_num)>>7;
//Lizard bank table @ FF94 //Lizard bank table @ FF94
//nes_cpu_wr( (0xFF94+bank), bank ); nes_cpu_wr( (0xFF94+bank), bank );
//HH85 //HH85
nes_cpu_wr( (0xFFE0+bank), bank ); //nes_cpu_wr( (0xFFE0+bank), bank );
//Mojon bank table @ FF94 //Mojon bank table @ FF94
//nes_cpu_wr( 0x800C, 0x00); //select first bank (only one with table) //nes_cpu_wr( 0x800C, 0x00); //select first bank (only one with table)
//nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank //nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank
@ -58,13 +89,69 @@ uint8_t dump_buff( buffer *buff ) {
nes_cpu_wr(0x8000, bank); //outer bank nes_cpu_wr(0x8000, bank); //outer bank
nes_cpu_wr(0x5000, 0x00); //chr reg select act like CNROM nes_cpu_wr(0x5000, 0x00); //chr reg select act like CNROM
} }
if (buff->mapper == EZNSF) {
//addrH &= 0b1000 1111 A14-12 must always be low
addrH &= 0x8F;
//write bank value to bank table
//page_num shift by 4 bits A12 >> A8(0)
bank = (buff->page_num)>>4;
nes_cpu_wr(0x5000, bank); //bank @ $8000-8FFF
}
buff->cur_byte = nes_cpu_page_rd_poll( buff->data, addrH, buff->id, buff->cur_byte = nes_cpu_page_rd_poll( buff->data, addrH, buff->id,
//id contains MSb of page when <256B buffer //id contains MSb of page when <256B buffer
buff->last_idx, ~FALSE ); buff->last_idx, ~FALSE );
break; break;
case CHRROM: //$0000 case CHRROM: //$0000
if (buff->mapper == NROM) {
buff->cur_byte = nes_ppu_page_rd_poll( buff->data, addrH, buff->id, buff->cur_byte = nes_ppu_page_rd_poll( buff->data, addrH, buff->id,
buff->last_idx, ~FALSE ); buff->last_idx, ~FALSE );
}
if (buff->mapper == CDREAM) {
//select bank
//8KB banks $0000-1FFF
//page_num shift by 5 bits A13 >> A8(0)
bank = (buff->page_num)>>5;
//write bank to register
//TODO account for bus conflicts
nes_cpu_wr(0xFFFF, bank<<4);
addrH &= 0x1F; //only A12-8 are directly addressable
buff->cur_byte = nes_ppu_page_rd_poll( buff->data, addrH, buff->id,
buff->last_idx, ~FALSE );
}
if (buff->mapper == DPROM) {
//select bank
//8KB banks $0000-1FFF
//page_num shift by 5 bits A13 >> A8(0)
bank = (buff->page_num)>>5;
//write bank to register
nes_ppu_wr(0x3FFF, bank);
addrH &= 0x1F; //only A12-8 are directly addressable
buff->cur_byte = nes_dualport_page_rd_poll( buff->data, addrH, buff->id,
buff->last_idx, ~FALSE );
}
if (buff->mapper == MMC1) {
//write bank value to bank table
//page_num shift by 4 bits A12 >> A8(0)
bank = (buff->page_num)>>4;
bank &= 0x1F; //only 5 bits in CHR regs
//LSb doesn't matter in 32KB mode
mmc1_wr(0x8000, 0x10, 1); //set to 4KB bank mode
mmc1_wr(0xA000, bank, 0); //write bank to CHR-ROM bank register
//TODO SXROM/SUROM require writting PRG-ROM MSb of address to CHR registers
addrH &= 0x0F; //only A11-8 are directly addressable
buff->cur_byte = nes_ppu_page_rd_poll( buff->data, addrH, buff->id,
buff->last_idx, ~FALSE );
}
break; break;
case PRGRAM: case PRGRAM:
addrH |= 0x60; //$6000 addrH |= 0x60; //$6000

435
firmware/source/flash.c
View File

@ -80,8 +80,9 @@ uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t
//select first bank for unlock sequence //select first bank for unlock sequence
//needs to be written to bank table! //needs to be written to bank table!
nes_cpu_wr( (0xCC84), 0x00 ); // nes_cpu_wr( (0xCC84), 0x00 );
// nes_cpu_wr( (0xE473), 0x00 ); nes_cpu_wr( (0xE473), 0x00 );
// nes_cpu_wr( (0xC000), 0x00 );
//wr_func( 0x5555, 0xAA ); //wr_func( 0x5555, 0xAA );
wr_func( unlock1, 0xAA ); wr_func( unlock1, 0xAA );
@ -92,8 +93,11 @@ uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t
//now need to select bank for the actual write! //now need to select bank for the actual write!
//but this write can't be applied to the PRG-ROM //but this write can't be applied to the PRG-ROM
nes_cpu_wr( (0xCC84+bank), bank ); // nes_cpu_wr( (0xCC84+bank), bank );
// nes_cpu_wr( (0xE473+bank), bank ); nes_cpu_wr( (0xE473+bank), bank );
// nes_cpu_wr( (0x8000+bank), bank );
//nes_cpu_wr( (0xC000+bank), bank );
// nes_cpu_wr( (0xFFC0+bank), bank );
wr_func( ((addrH<<8)| n), buff->data[n] ); wr_func( ((addrH<<8)| n), buff->data[n] );
@ -123,6 +127,109 @@ uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t
} }
uint8_t write_page_bank_map30( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlock2, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{
uint16_t cur = buff->cur_byte;
uint8_t n = buff->cur_byte;
uint8_t read;
while ( cur <= buff->last_idx ) {
//select first bank for unlock sequence
//wr_func( 0x5555, 0xAA );
nes_cpu_wr( 0xC000, 0x01 );
wr_func( unlock1, 0xAA );
//wr_func( 0x2AAA, 0x55 );
nes_cpu_wr( 0xC000, 0x00 );
wr_func( unlock2, 0x55 );
//wr_func( 0x5555, 0xA0 );
nes_cpu_wr( 0xC000, 0x01 );
wr_func( unlock1, 0xA0 );
//now need to select bank for the actual write!
nes_cpu_wr( 0xC000, bank );
wr_func( ((addrH<<8)| n), buff->data[n] );
do {
usbPoll();
read = rd_func((addrH<<8)|n);
} while( read != rd_func((addrH<<8)|n) );
//retry if write failed
//this helped but still seeing similar fails to dumps
if (read == buff->data[n]) {
n++;
cur++;
LED_IP_PU();
LED_LO();
} else {
LED_OP();
LED_HI();
}
}
buff->cur_byte = n;
return SUCCESS;
}
uint8_t write_page_mmc1( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlock2, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{
uint16_t cur = buff->cur_byte;
uint8_t n = buff->cur_byte;
uint8_t read;
while ( cur <= buff->last_idx ) {
mmc1_wr(0x8000, 0x10, 0); //32KB mode
//IDK why, but somehow only the first byte gets programmed when ROM A14=1
//so somehow it's getting out of 32KB mode for follow on bytes..
//even though we reset to 32KB mode after the corrupting final write
wr_func( unlock1, 0xAA );
wr_func( unlock2, 0x55 );
wr_func( unlock1, 0xA0 );
wr_func( ((addrH<<8)| n), buff->data[n] );
//writes to flash are to $8000-FFFF so any register could have been corrupted and shift register may be off
//In reality MMC1 should have blocked all subsequent writes, so maybe only the CHR reg2 got corrupted..?
mmc1_wr(0x8000, 0x10, 1); //32KB mode
mmc1_wr(0xE000, bank, 0); //reset shift register, and bank register
do {
usbPoll();
read = rd_func((addrH<<8)|n);
} while( read != rd_func((addrH<<8)|n) );
//retry if write failed
//this helped but still seeing similar fails to dumps
if (read == buff->data[n]) {
n++;
cur++;
LED_IP_PU();
LED_LO();
} else {
mmc1_wr(0x8000, 0x10, 1); //32KB mode
mmc1_wr(0xE000, bank, 0); //reset shift register, and bank register
LED_OP();
LED_HI();
}
}
buff->cur_byte = n;
return SUCCESS;
}
uint8_t write_page_a53( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func ) uint8_t write_page_a53( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{ {
uint16_t cur = buff->cur_byte; uint16_t cur = buff->cur_byte;
@ -189,18 +296,19 @@ uint8_t write_page_a53( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr
//retry if write failed //retry if write failed
//this helped but still seeing similar fails to dumps //this helped but still seeing similar fails to dumps
// if (read == buff->data[n]) { if (read == buff->data[n]) {
n++; n++;
cur++; cur++;
// LED_IP_PU(); LED_IP_PU();
// LED_LO(); LED_LO();
// } else { } else {
//// nes_cpu_wr(0x5000, 0x81); //outer reg select mode //kaz6 final needs a retry, but proto doesn't...
//// nes_cpu_wr(0x8000, bank); //outer bank nes_cpu_wr(0x5000, 0x81); //outer reg select mode
//// nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes nes_cpu_wr(0x8000, bank); //outer bank
// LED_OP(); nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
// LED_HI(); LED_OP();
// } LED_HI();
}
} }
@ -217,6 +325,74 @@ uint8_t write_page_a53( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr
} }
uint8_t write_page_tssop( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{
uint16_t cur = buff->cur_byte;
uint8_t n = buff->cur_byte;
uint8_t read;
// extern operation_info *oper_info;
//
//enter unlock bypass mode
wr_func( 0x8AAA, 0xAA );
wr_func( 0x8555, 0x55 );
wr_func( 0x8AAA, 0x20 );
while ( cur <= buff->last_idx ) {
//TODO FIX THIS! It shouldn't be needed!
//but for some reason the mapper is loosing it's setting for $5000 register to
//permit flash writes. Many writes go through, but at somepoint it gets lost..
//maybe the best fix it to require address to be equal to $5555 to write to flash enable register..
//but for now, this rewrite hack solves the issue.
//nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
//AVR didn't need this patch so maybe is a speed issue
//stmadapter didn't have problems either..
//added time delay before m2 rising edge and it didn't change anything for stm6
// curaddresswrite( 0xA0 ); //gained ~3KBps (59.13KBps) inl6 with v3.0 proto
wr_func( ((addrH<<8)| n), 0xA0 );
wr_func( ((addrH<<8)| n), buff->data[n] );
do {
usbPoll();
read = rd_func((addrH<<8)|n);
} while( read != rd_func((addrH<<8)|n) );
//retry if write failed
//this helped but still seeing similar fails to dumps
if (read == buff->data[n]) {
n++;
cur++;
LED_IP_PU();
LED_LO();
} else {
//kaz6 final needs a retry, but proto doesn't...
// nes_cpu_wr(0x5000, 0x81); //outer reg select mode
// nes_cpu_wr(0x8000, bank); //outer bank
// nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
LED_OP();
LED_HI();
}
}
buff->cur_byte = n;
//exit unlock bypass mode
wr_func( 0x8000, 0x90 );
wr_func( 0x8000, 0x00 );
//reset the flash chip, supposed to exit too
wr_func( 0x8000, 0xF0 );
return SUCCESS;
}
uint8_t write_page_chr( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func ) uint8_t write_page_chr( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{ {
uint16_t cur = buff->cur_byte; uint16_t cur = buff->cur_byte;
@ -279,10 +455,131 @@ uint8_t write_page_chr( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr
} }
uint8_t write_page_chr_cdream( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{
uint16_t cur = buff->cur_byte;
uint8_t n = buff->cur_byte;
uint8_t read;
// extern operation_info *oper_info;
while ( cur <= buff->last_idx ) {
//write unlock sequence
//need to make address and unlock data variable
//best for host to communcate these values
//actual value is part mapper dependent and part flash dependent
//mapper controlled address bits dictate where split is
//32KB banking A14-0 NES ctl, A15+ mapper ctl "bank" NROM, BNROM, ANROM
//addrH_dmask = 0b0111 1111 directly addressable addrH bits
//page2bankshft = A14->A8 = 7 shifts (equal to number of set bits in addrH_mask
//16KB banking A13-0 NES ctl, A14+ mapper ctl "bank" UxROM, MMC1
//addrH_dmask = 0b0011 1111
//page2bankshft = A13->A8 = 6 shifts
// 8KB banking A12-0 NES ctl, A13+ mapper ctl "bank" MMC3, FME7
//addrH_dmask = 0b0001 1111
//page2bankshft = A12->A8 = 5 shifts
// 4KB banking A11-0 NES ctl, A12+ mapper ctl "bank" ezNSF
//addrH_dmask = 0b0000 1111
//page2bankshft = A11->A8 = 4 shifts
nes_cpu_wr(0x8000, 0x20);
wr_func( 0x1555, 0xAA );
// wr_func( oper_info->unlock1_AH, oper_info->unlock1_AL, oper_info->unlock1_data );
nes_cpu_wr(0x8000, 0x10);
wr_func( 0x0AAA, 0x55 );
// wr_func( oper_info->unlock2_AH, oper_info->unlock2_AL, oper_info->unlock2_data );
nes_cpu_wr(0x8000, 0x20);
wr_func( 0x1555, 0xA0 );
// wr_func( oper_info->command_AH, oper_info->command_AL, oper_info->command1_data );
nes_cpu_wr(0x8000, bank<<4);
wr_func( ((addrH<<8)| n), buff->data[n] );
//wr_func( ((addrH<<8)| n), buff->page_num );
//wr_func( ((addrH<<8)| n), addrH);
do {
usbPoll();
read = rd_func((addrH<<8)|n);
} while( read != rd_func((addrH<<8)|n) );
//TODO verify byte is value that was trying to be flashed
//move on to next byte
//n++;
//cur++;
if (read == buff->data[n]) {
n++;
cur++;
LED_IP_PU();
LED_LO();
} else {
LED_OP();
LED_HI();
}
}
buff->cur_byte = n;
return SUCCESS;
}
uint8_t write_page_dualport( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{
uint16_t cur = buff->cur_byte;
uint8_t n = buff->cur_byte;
uint8_t read;
// extern operation_info *oper_info;
//enter unlock bypass mode
wr_func( 0x0AAA, 0xAA );
wr_func( 0x0555, 0x55 );
wr_func( 0x0AAA, 0x20 );
while ( cur <= buff->last_idx ) {
wr_func( ((addrH<<8)| n), 0xA0 );
wr_func( ((addrH<<8)| n), buff->data[n] );
do {
usbPoll();
read = rd_func((addrH<<8)|n);
} while( read != rd_func((addrH<<8)|n) );
//TODO verify byte is value that was trying to be flashed
//move on to next byte
//n++;
//cur++;
if (read == buff->data[n]) {
n++;
cur++;
LED_IP_PU();
LED_LO();
} else {
LED_OP();
LED_HI();
}
}
buff->cur_byte = n;
//exit unlock bypass mode
wr_func( 0x0000, 0x90 );
wr_func( 0x0000, 0x00 );
//reset the flash chip, supposed to exit too
wr_func( 0x0000, 0xF0 );
return SUCCESS;
}
//#define PRGM_MODE() swim_wotf(SWIM_HS, 0x500F, 0x40) //#define PRGM_MODE() swim_wotf(SWIM_HS, 0x500F, 0x40)
//#define PLAY_MODE() swim_wotf(SWIM_HS, 0x500F, 0x00) //#define PLAY_MODE() swim_wotf(SWIM_HS, 0x500F, 0x00)
#define PRGM_MODE() EXP0_LO() //#define PRGM_MODE() EXP0_LO()
#define PLAY_MODE() EXP0_HI() //#define PLAY_MODE() EXP0_HI()
#define PRGM_MODE() NOP()
#define PLAY_MODE() NOP()
uint8_t write_page_snes( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func ) uint8_t write_page_snes( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
{ {
@ -313,9 +610,9 @@ uint8_t write_page_snes( uint8_t bank, uint8_t addrH, buffer *buff, write_funcpt
NOP(); NOP();
//enter unlock bypass mode //enter unlock bypass mode
wr_func( 0x0AAA, 0xAA ); wr_func( 0x8AAA, 0xAA );
wr_func( 0x0555, 0x55 ); wr_func( 0x8555, 0x55 );
wr_func( 0x0AAA, 0x20 ); wr_func( 0x8AAA, 0x20 );
while ( cur <= buff->last_idx ) { while ( cur <= buff->last_idx ) {
@ -460,25 +757,27 @@ uint8_t write_page_snes( uint8_t bank, uint8_t addrH, buffer *buff, write_funcpt
//retry if write failed //retry if write failed
//this helped but still seeing similar fails to dumps //this helped but still seeing similar fails to dumps
if (read == buff->data[n]) {
n++; n++;
cur++; cur++;
LED_IP_PU(); // if (read == buff->data[n]) {
LED_LO(); // //n++;
} else { // //cur++;
LED_OP(); // LED_IP_PU();
LED_HI(); // LED_LO();
} // } else {
// LED_OP();
// LED_HI();
// }
} }
buff->cur_byte = n; buff->cur_byte = n;
//exit unlock bypass mode //exit unlock bypass mode
wr_func( 0x0000, 0x90 ); wr_func( 0x8000, 0x90 );
wr_func( 0x0000, 0x00 ); wr_func( 0x8000, 0x00 );
//reset the flash chip, supposed to exit too //reset the flash chip, supposed to exit too
wr_func( 0x0000, 0xF0 ); wr_func( 0x8000, 0xF0 );
//exit program mode //exit program mode
//EXP0_HI(); //EXP0_HI();
@ -517,6 +816,16 @@ uint8_t flash_buff( buffer *buff ) {
if (buff->mapper == NROM) { if (buff->mapper == NROM) {
write_page( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd ); write_page( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
} }
if (buff->mapper == MMC1) {
//write bank value
//page_num shift by 6 bits A15 >> A9(1)
bank = (buff->page_num)>>6; //LSbit doesn't matter in 32KB mode
bank &= 0x0F; //only 4 bits in PRG register
mmc1_wr(0x8000, 0x10, 1); //ensure 32KB mode
mmc1_wr(0xE000, bank, 0); //write bank to PRG-ROM bank register
//TODO SXROM/SUROM require writting PRG-ROM MSb of address to CHR registers
write_page_mmc1( bank, (0x80 | addrH), 0xD555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
}
if (buff->mapper == UxROM) { if (buff->mapper == UxROM) {
//addrH &= 0b1011 1111 A14 must always be low //addrH &= 0b1011 1111 A14 must always be low
addrH &= 0x3F; addrH &= 0x3F;
@ -527,19 +836,41 @@ uint8_t flash_buff( buffer *buff ) {
//bank gets written inside flash algo //bank gets written inside flash algo
write_page_bank( bank, addrH, 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd ); write_page_bank( bank, addrH, 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
} }
if (buff->mapper == MAP30) {
//addrH &= 0b1011 1111 A14 must always be low
addrH &= 0x3F;
addrH |= 0x80;
//write bank value
//page_num shift by 6 bits A14 >> A8(0)
bank = buff->page_num >> 6;
//bank gets written inside flash algo
write_page_bank_map30( bank, addrH, 0x9555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
}
if ((buff->mapper == BxROM) || (buff->mapper == CDREAM)) { if ((buff->mapper == BxROM) || (buff->mapper == CDREAM)) {
//write bank value //write bank value
//page_num shift by 7 bits A15 >> A8(0) //page_num shift by 7 bits A15 >> A8(0)
bank = buff->page_num >> 7; bank = buff->page_num >> 7;
//Lizard banktable location //Lizard banktable location
//nes_cpu_wr( (0xFF94+bank), bank ); nes_cpu_wr( (0xFF94+bank), bank );
//hh85 //hh85
nes_cpu_wr( (0xFFE0+bank), bank ); //nes_cpu_wr( (0xFFE0+bank), bank );
//Mojontales //Mojontales
//nes_cpu_wr( 0x800C, 0x00); //select first bank (only bank with table) //nes_cpu_wr( 0x800C, 0x00); //select first bank (only bank with table)
//nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank //nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank
write_page( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd ); write_page( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
} }
if (buff->mapper == CNINJA) {
//addrH &= 0b1001 1111 A14-13 must always be low
addrH &= 0x1F;
addrH |= 0x80;
//write bank value
//page_num shift by 5 bits A13 >> A8(0)
bank = buff->page_num >> 5;
nes_cpu_wr( (0x6000), 0xA5 ); //select desired bank
nes_cpu_wr( (0xFFFF), bank ); //select desired bank
write_page( 0, addrH, 0xD555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
}
if (buff->mapper == A53) { if (buff->mapper == A53) {
//write bank value to bank table //write bank value to bank table
//page_num shift by 7 bits A15 >> A8(0) //page_num shift by 7 bits A15 >> A8(0)
@ -556,13 +887,51 @@ uint8_t flash_buff( buffer *buff ) {
//write_page( 0, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd ); //write_page( 0, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd );
//break; //break;
//WORKS PLCC Action53: //WORKS PLCC Action53:
//write_page( bank, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd ); //had problems later not all bytes getting programmed..
//write_page( bank, (0x80 | addrH), 0xD555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
//TSSOP-28 action53: //TSSOP-28 action53:
write_page_a53( bank, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd ); write_page_a53( bank, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd );
} }
if (buff->mapper == EZNSF) {
//addrH &= 0b1000 1111 A14-12 must always be low
addrH &= 0x8F;
//write bank value to bank table
//page_num shift by 4 bits A12 >> A8(0)
bank = (buff->page_num)>>4;
nes_cpu_wr(0x5000, bank); //bank @ $8000-8FFF
write_page_tssop( bank, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd );
}
break; break;
case CHRROM: //$0000 case CHRROM: //$0000
if (buff->mapper == NROM) {
write_page_chr( 0, addrH, buff, nes_ppu_wr, nes_ppu_rd ); write_page_chr( 0, addrH, buff, nes_ppu_wr, nes_ppu_rd );
}
if (buff->mapper == CDREAM) {
//select bank
//8KB banks $0000-1FFF
//page_num shift by 5 bits A13 >> A8(0)
bank = (buff->page_num)>>5;
//write bank to register
//done inside write routine
//nes_cpu_wr(0x8000, bank<<4);
addrH &= 0x1F; //only A12-8 are directly addressable
write_page_chr_cdream( bank, addrH, buff, nes_ppu_wr, nes_ppu_rd );
}
if (buff->mapper == DPROM) {
//select bank
//8KB banks $0000-1FFF
//page_num shift by 5 bits A13 >> A8(0)
bank = (buff->page_num)>>5;
//write bank to register
nes_ppu_wr(0x3FFF, bank);
addrH &= 0x1F; //only A12-8 are directly addressable
write_page_dualport( 0, addrH, buff, nes_dualport_wr, nes_dualport_rd );
}
break; break;
case PRGRAM: case PRGRAM:
//addrH |= 0x60; //$6000 //addrH |= 0x60; //$6000
@ -576,6 +945,8 @@ uint8_t flash_buff( buffer *buff ) {
//A15 high (LOROM) //A15 high (LOROM)
//A23-16 page_num[14-8] //A23-16 page_num[14-8]
HADDR_SET( (buff->page_num)>>7 ); HADDR_SET( (buff->page_num)>>7 );
//clear any reset state
//EXP0_HI();
write_page_snes( 0, addrH, buff, snes_rom_wr, snes_rom_rd ); write_page_snes( 0, addrH, buff, snes_rom_wr, snes_rom_rd );
case SNESRAM: case SNESRAM:
//warn addrX = ((buff->page_num)>>8); //warn addrX = ((buff->page_num)>>8);

6
firmware/source/io.c
View File

@ -71,7 +71,7 @@ void io_reset()
//pull up control port //pull up control port
CTL_ENABLE(); CTL_ENABLE();
MCO_IP_PU(); M2_IP_PU();
ROMSEL_IP_PU(); ROMSEL_IP_PU();
PRGRW_IP_PU(); PRGRW_IP_PU();
CSRD_IP_PU(); CSRD_IP_PU();
@ -128,8 +128,8 @@ void nes_init()
ROMSEL_OP(); ROMSEL_OP();
ROMSEL_HI(); ROMSEL_HI();
//WRAM (and state of m2 during first half of CPU cycle) //WRAM (and state of m2 during first half of CPU cycle)
MCO_OP(); M2_OP();
MCO_LO(); M2_LO();
//CPU RD //CPU RD
PRGRW_OP(); PRGRW_OP();
PRGRW_HI(); PRGRW_HI();

19
firmware/source/main.c
View File

@ -59,6 +59,9 @@ int main(void)
//Change system clock as needed //Change system clock as needed
init_clock(); init_clock();
//now enable GPIO and set
//trying to move to 48Mhz clock for all STM32 cores //trying to move to 48Mhz clock for all STM32 cores
//If >24Mhz SYSCLK, must add wait state to flash //If >24Mhz SYSCLK, must add wait state to flash
//can also enable prefetch buffer //can also enable prefetch buffer
@ -87,6 +90,22 @@ int main(void)
//intialize i/o and LED to pullup state //intialize i/o and LED to pullup state
io_reset(); io_reset();
//this is just a quick hack to allow measuring HSE with a scope w/o loading the circuit with probes.
//#define DRIVE_MCO
#ifdef DRIVE_MCO
//drive HSE (8Mhz) divided by 8 = 1Mhz for crystal load capacitor calibration
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCOPRE) | RCC_CFGR_MCOPRE_DIV8; /* MCO prescaler = div 8 */
//RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCOPRE) | RCC_CFGR_MCOPRE_DIV16; /* MCO prescaler = div 16 */
RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_MCO) | RCC_CFGR_MCO_HSE; /* MCO source HSE */
//enable GPIO pin PA8 MCO AF0
//RCC->AHBENR |= RCC_AHBENR_GPIOAEN;
//CTL_ENABLE();
nes_init();
//GPIOA->MODER = MODER_AF << (2*8U); //set PA8 to AF
GPIOA->MODER = 0x28020000; //set PA14, PA13, (SWD) & PA8 (MCO) to AF
//AF0 is the default value of GPIOx_AFRH/L registers so MCO is already selected as AF in use
#endif
//initialize jtag engine to be off //initialize jtag engine to be off
pbje_status = PBJE_OFF; pbje_status = PBJE_OFF;

339
firmware/source/nes.c
View File

@ -38,14 +38,21 @@ uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
case NES_CPU_WR: case NES_CPU_WR:
nes_cpu_wr( operand, miscdata ); nes_cpu_wr( operand, miscdata );
break; break;
case NES_DUALPORT_WR:
nes_dualport_wr( operand, miscdata );
break;
// case DISCRETE_EXP0_MAPPER_WR: // case DISCRETE_EXP0_MAPPER_WR:
// discrete_exp0_mapper_wr( operand, miscdata ); // discrete_exp0_mapper_wr( operand, miscdata );
// break; // break;
case NES_MMC1_WR:
mmc1_wr( operand, miscdata, 0 );
break;
//8bit return values: //8bit return values:
// case EMULATE_NES_CPU_RD: case EMULATE_NES_CPU_RD:
// *data = emulate_nes_cpu_rd( addrH, addrL ); rdata[RD_LEN] = BYTE_LEN;
// break; rdata[RD0] = emulate_nes_cpu_rd( operand );
break;
case NES_CPU_RD: case NES_CPU_RD:
rdata[RD_LEN] = BYTE_LEN; rdata[RD_LEN] = BYTE_LEN;
rdata[RD0] = nes_cpu_rd( operand ); rdata[RD0] = nes_cpu_rd( operand );
@ -54,6 +61,10 @@ uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
rdata[RD_LEN] = BYTE_LEN; rdata[RD_LEN] = BYTE_LEN;
rdata[RD0] = nes_ppu_rd( operand ); rdata[RD0] = nes_ppu_rd( operand );
break; break;
case NES_DUALPORT_RD:
rdata[RD_LEN] = BYTE_LEN;
rdata[RD0] = nes_dualport_rd( operand );
break;
case CIRAM_A10_MIRROR: case CIRAM_A10_MIRROR:
rdata[RD_LEN] = BYTE_LEN; rdata[RD_LEN] = BYTE_LEN;
rdata[RD0] = ciram_a10_mirroring( ); rdata[RD0] = ciram_a10_mirroring( );
@ -148,7 +159,7 @@ void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
// DATA_SET(data); // DATA_SET(data);
// //
// //set M2 and /ROMSEL // //set M2 and /ROMSEL
// MCO_HI(); // M2_HI();
// if( addr >= 0x8000 ) { //addressing cart rom space // if( addr >= 0x8000 ) { //addressing cart rom space
// ROMSEL_LO(); //romsel trails M2 during CPU operations // ROMSEL_LO(); //romsel trails M2 during CPU operations
// } // }
@ -158,7 +169,7 @@ void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
// NOP(); // NOP();
// //
// //latch data to cart memory/mapper // //latch data to cart memory/mapper
// MCO_LO(); // M2_LO();
// ROMSEL_HI(); // ROMSEL_HI();
// //
// //retore PRG R/W to default // //retore PRG R/W to default
@ -209,67 +220,66 @@ void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
//} //}
//
// /* Desc:Emulate NES CPU Read as best possible /* Desc:Emulate NES CPU Read as best possible
// * decode A15 from addrH to set /ROMSEL as expected * decode A15 from addrH to set /ROMSEL as expected
// * float EXP0 * float EXP0
// * toggle M2 as NES would * toggle M2 as NES would
// * insert some NOP's in to be slow like NES * insert some NOP's in to be slow like NES
// * Note:not the fastest read operation * Note:not the fastest read operation
// * Pre: nes_init() setup of io pins * Pre: nes_init() setup of io pins
// * Post:address left on bus * Post:address left on bus
// * data bus left clear * data bus left clear
// * EXP0 left floating * EXP0 left floating
// * Rtn: Byte read from PRG-ROM at addrHL * Rtn: Byte read from PRG-ROM at addrHL
// */ */
// uint8_t emulate_nes_cpu_rd( uint8_t addrH, uint8_t addrL ) uint8_t emulate_nes_cpu_rd( uint16_t addr )
// { {
// uint8_t read; //return value uint8_t read; //return value
//
// //m2 should be low as it aids in disabling WRAM //m2 should be low as it aids in disabling WRAM
// //this is also m2 state at beginging of CPU cycle //this is also m2 state at beginging of CPU cycle
// //all these pins should already be in this state, but //all these pins should already be in this state, but
// //go ahead and setup just to be sure since we're trying //go ahead and setup just to be sure since we're trying
// //to be as accurate as possible //to be as accurate as possible
// _EXP0_FLT(); //this could have been left pulled up EXP0_IP_FL(); //this could have been left pulled up
// _M2_LO(); //start of CPU cycle M2_LO(); //start of CPU cycle
// _ROMSEL_HI(); //trails M2 ROMSEL_HI(); //trails M2
// _PRGRW_RD(); //happens just after M2 PRGRW_HI(); //happens just after M2
//
// //set address bus //set address bus
// ADDR_OUT = addrL; ADDR_SET(addr);
// _ADDRH_SET(addrH);
// //couple NOP's to wait a bit
// //couple NOP's to wait a bit NOP();
// NOP(); NOP();
// NOP();
// //set M2 and /ROMSEL
// //set M2 and /ROMSEL if( addr >= 0x8000 ) { //addressing cart rom space
// if( addrH >= 0x80 ) { //addressing cart rom space M2_HI();
// _M2_HI(); ROMSEL_LO(); //romsel trails M2 during CPU operations
// _ROMSEL_LO(); //romsel trails M2 during CPU operations } else {
// } else { M2_HI();
// _M2_HI(); }
// }
// //couple more NOP's waiting for data
// //couple more NOP's waiting for data NOP();
// NOP(); NOP();
// NOP(); NOP();
// NOP(); NOP();
// NOP(); NOP();
// NOP(); NOP();
// NOP();
// //latch data
// //latch data DATA_RD(read);
// read = DATA_IN;
// //return bus to default
// //return bus to default M2_LO();
// _M2_LO(); ROMSEL_HI();
// _ROMSEL_HI();
// return read;
// return read; }
// }
//
/* Desc:NES CPU Read without being so slow /* Desc:NES CPU Read without being so slow
* decode A15 from addrH to set /ROMSEL as expected * decode A15 from addrH to set /ROMSEL as expected
* float EXP0 * float EXP0
@ -288,7 +298,7 @@ uint8_t nes_cpu_rd( uint16_t addr )
ADDR_SET(addr); ADDR_SET(addr);
//set M2 and /ROMSEL //set M2 and /ROMSEL
MCO_HI(); M2_HI();
if( addr >= 0x8000 ) { //addressing cart rom space if( addr >= 0x8000 ) { //addressing cart rom space
ROMSEL_LO(); //romsel trails M2 during CPU operations ROMSEL_LO(); //romsel trails M2 during CPU operations
} }
@ -305,7 +315,7 @@ uint8_t nes_cpu_rd( uint16_t addr )
DATA_RD(read); DATA_RD(read);
//return bus to default //return bus to default
MCO_LO(); M2_LO();
ROMSEL_HI(); ROMSEL_HI();
return read; return read;
@ -346,7 +356,7 @@ void nes_cpu_wr( uint16_t addr, uint8_t data )
DATA_SET(data); DATA_SET(data);
//set M2 and /ROMSEL //set M2 and /ROMSEL
MCO_HI(); M2_HI();
if( addr >= 0x8000 ) { //addressing cart rom space if( addr >= 0x8000 ) { //addressing cart rom space
ROMSEL_LO(); //romsel trails M2 during CPU operations ROMSEL_LO(); //romsel trails M2 during CPU operations
} }
@ -356,7 +366,7 @@ void nes_cpu_wr( uint16_t addr, uint8_t data )
NOP(); NOP();
//latch data to cart memory/mapper //latch data to cart memory/mapper
MCO_LO(); M2_LO();
ROMSEL_HI(); ROMSEL_HI();
//retore PRG R/W to default //retore PRG R/W to default
@ -366,6 +376,7 @@ void nes_cpu_wr( uint16_t addr, uint8_t data )
DATA_IP(); DATA_IP();
} }
/* Desc:NES PPU Read /* Desc:NES PPU Read
* decode A13 from addrH to set /A13 as expected * decode A13 from addrH to set /A13 as expected
* Pre: nes_init() setup of io pins * Pre: nes_init() setup of io pins
@ -445,6 +456,87 @@ void nes_ppu_wr( uint16_t addr, uint8_t data )
} }
/* Desc:NES dual port Read from the PPU
* /A13 as ignored
* Pre: nes_init() setup of io pins
* Post:address left on bus
* data bus left clear
* Rtn: Byte read from CHR-ROM/RAM at addrHL
*/
uint8_t nes_dualport_rd( uint16_t addr )
{
uint8_t read; //return value
ADDR_SET( addr );
//enable data path
M2_HI(); //M2 is kinda like R/W setting direction
ROMSEL_LO(); //enable data buffers
//data should now be driven on the bus but invalid
//set CHR /RD and /WR
CSRD_LO();
//couple more NOP's waiting for data
//zero nop's returned previous databus value
NOP(); //one nop got most of the bits right
NOP(); //two nop got all the bits right
NOP(); //add third nop for some extra
//latch data
DATA_RD(read);
//return bus to default
CSRD_HI();
M2_LO();
ROMSEL_HI();
return read;
}
/* Desc:NES DUALPORT Write
* /A13 ignored
* Pre: nes_init() setup of io pins
* Post:data written to addrHL
* address left on bus
* data bus left clear
* Rtn: None
*/
void nes_dualport_wr( uint16_t addr, uint8_t data )
{
ADDR_SET( addr );
//enable data path
M2_LO(); //M2 is kinda like R/W setting direction
ROMSEL_LO(); //enable data buffers
//data should now be driven on the bus but invalid
//put data on bus
DATA_OP();
DATA_SET(data);
NOP();
//set CHR /RD and /WR
CSWR_LO();
//might need to wait longer for some carts...
NOP(); //one can't hurt
//latch data to memory
CSWR_HI();
//clear data bus
DATA_IP();
ROMSEL_HI();
}
/* Desc:PPU CIRAM A10 NT arrangement sense /* Desc:PPU CIRAM A10 NT arrangement sense
* Toggle A11 and A10 and read back CIRAM A10 * Toggle A11 and A10 and read back CIRAM A10
* report back if vert/horiz/1scnA/1scnB * report back if vert/horiz/1scnA/1scnB
@ -460,17 +552,20 @@ uint8_t ciram_a10_mirroring( void )
{ {
uint16_t readV, readH; uint16_t readV, readH;
//set A11, clear A10
//ADDRH(A11_BYTE); setting A11 in this manner doesn't work for some reason..
ADDR_SET(0x0800);
CIA10_RD(readH);
//set A10, clear A11 //set A10, clear A11
ADDRH(A10_BYTE); ADDRH(A10_BYTE);
//ADDR_SET(0x0400);
CIA10_RD(readV); CIA10_RD(readV);
//set A11, clear A10
ADDRH(A11_BYTE);
CIA10_RD(readH);
//if CIRAM A10 was always low -> 1 screen A //if CIRAM A10 was always low -> 1 screen A
if ((readV==0) & (readH==0)) return MIR_1SCNA; if ((readV==0) & (readH==0)) return MIR_1SCNA;
//if CIRAM A10 was always hight -> 1screen B //if CIRAM A10 was always high -> 1 screen B
if ((readV!=0) & (readH!=0)) return MIR_1SCNB; if ((readV!=0) & (readH!=0)) return MIR_1SCNB;
//if CIRAM A10 toggled with A10 -> Vertical mirroring, horizontal arrangement //if CIRAM A10 toggled with A10 -> Vertical mirroring, horizontal arrangement
if ((readV!=0) & (readH==0)) return MIR_VERT; if ((readV!=0) & (readH==0)) return MIR_VERT;
@ -503,7 +598,7 @@ uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8
ADDRH(addrH); ADDRH(addrH);
//set M2 and /ROMSEL //set M2 and /ROMSEL
MCO_HI(); M2_HI();
if( addrH >= 0x80 ) { //addressing cart rom space if( addrH >= 0x80 ) { //addressing cart rom space
ROMSEL_LO(); //romsel trails M2 during CPU operations ROMSEL_LO(); //romsel trails M2 during CPU operations
} }
@ -530,7 +625,7 @@ uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8
} }
//return bus to default //return bus to default
MCO_LO(); M2_LO();
ROMSEL_HI(); ROMSEL_HI();
//return index of last byte read //return index of last byte read
@ -590,3 +685,95 @@ uint8_t nes_ppu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8
//return index of last byte read //return index of last byte read
return i; return i;
} }
/* Desc:NES DUAL PORT PPU Page Read with optional USB polling
* /A13 ignored
* if poll is true calls usbdrv.h usbPoll fuction
* this is needed to keep from timing out when double buffering usb data
* Pre: nes_init() setup of io pins
* num_bytes can't exceed 256B page boundary
* Post:address left on bus
* data bus left clear
* data buffer filled starting at first for len number of bytes
* Rtn: Index of last byte read
*/
uint8_t nes_dualport_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
{
uint8_t i;
//ignore /A13, board doesn't see it anyway
ADDRH(addrH);
//now that data bus is no longer needed,
//can enable data path out of cart
M2_HI();
ROMSEL_LO();
//set CHR /RD and /WR
CSRD_LO();
//set lower address bits
ADDRL(first); //doing this prior to entry and right after latching
NOP(); //adding extra NOP as it was needed on PRG
//gives longest delay between address out and latching data
for( i=0; i<=len; i++ ) {
//couple more NOP's waiting for data
if ( poll == FALSE ) {
NOP(); //one prob good enough considering the if/else
NOP();
} else {
usbPoll();
}
//latch data
DATA_RD(data[i]);
//set lower address bits
first ++;
ADDRL(first);
}
//return bus to default
CSRD_HI();
M2_LO();
ROMSEL_HI();
//return index of last byte read
return i;
}
/* Desc:NES MMC1 Write
* write to entirety of MMC1 register
* address selects register that's written to
* address must be >= $8000 where registers are located
* Pre: nes_init() setup of io pins
* MMC1 shift register has been reset by writting with D7 set
* bit7 must be clear, else the shift register will be reset
* Post:MMC1 register contains value provided
* address left on bus
* data left on bus, but pullup only
* Rtn: None
*/
void mmc1_wr( uint16_t addr, uint8_t data, uint8_t reset )
{
uint8_t i;
//reset shift register if requested
if( reset ) {
nes_cpu_rd(0x8000);
nes_cpu_wr(0x8000, 0x80);
}
//5 bits in register D0-4, so 5 total writes through D0
for( i=0; i<5; i++) {
//MMC1 ignores all but the first write, so perform a read first
nes_cpu_rd(addr);
nes_cpu_wr(addr, data);
data = data >> 1;
}
return;
}

6
firmware/source/nes.h
View File

@ -10,14 +10,18 @@ uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data ); void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data );
//void discrete_exp0_mapper_wr( uint16_t addr, uint8_t data ); //void discrete_exp0_mapper_wr( uint16_t addr, uint8_t data );
//uint8_t emulate_nes_cpu_rd( uint8_t addrH, uint8_t addrL ); uint8_t emulate_nes_cpu_rd( uint16_t addr );
uint8_t nes_cpu_rd( uint16_t addr ); uint8_t nes_cpu_rd( uint16_t addr );
void nes_cpu_wr( uint16_t addr, uint8_t data ); void nes_cpu_wr( uint16_t addr, uint8_t data );
uint8_t nes_ppu_rd( uint16_t addr ); uint8_t nes_ppu_rd( uint16_t addr );
void nes_ppu_wr( uint16_t addr, uint8_t data ); void nes_ppu_wr( uint16_t addr, uint8_t data );
uint8_t nes_dualport_rd( uint16_t addr );
void nes_dualport_wr( uint16_t addr, uint8_t data );
uint8_t ciram_a10_mirroring( void ); uint8_t ciram_a10_mirroring( void );
uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t last, uint8_t poll ); uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t last, uint8_t poll );
uint8_t nes_ppu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t last, uint8_t poll ); uint8_t nes_ppu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t last, uint8_t poll );
uint8_t nes_dualport_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll );
void mmc1_wr( uint16_t addr, uint8_t data, uint8_t reset );
#define A10_BYTE 0x04 #define A10_BYTE 0x04
#define A11_BYTE 0x08 #define A11_BYTE 0x08

14
firmware/source/pinport.h
View File

@ -16,13 +16,13 @@ uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_
// CONTROL (CTL) PORT PINS // CONTROL (CTL) PORT PINS
//////////////////////////////// ////////////////////////////////
// PC0 "MCO" // PC0 "M2"
#define MCO_IP_PU() CTL_IP_PU(MCObank, MCO) #define M2_IP_PU() CTL_IP_PU(M2bank, M2)
#define MCO_IP_FL() CTL_IP_FL(MCObank, MCO) #define M2_IP_FL() CTL_IP_FL(M2bank, M2)
#define MCO_OP() CTL_OP(MCObank, MCO) #define M2_OP() CTL_OP(M2bank, M2)
#define MCO_LO() CTL_SET_LO(MCObank, MCO) #define M2_LO() CTL_SET_LO(M2bank, M2)
#define MCO_HI() CTL_SET_HI(MCObank, MCO) #define M2_HI() CTL_SET_HI(M2bank, M2)
#define MCO_RD(val) CTL_RD(MCObank, MCO, val) #define M2_RD(val) CTL_RD(M2bank, M2, val)
// PC1 "ROMSEL" // PC1 "ROMSEL"
#define ROMSEL_IP_PU() CTL_IP_PU(ROMSELbank, ROMSEL) #define ROMSEL_IP_PU() CTL_IP_PU(ROMSELbank, ROMSEL)

215
firmware/source/pinport_al.h
View File

@ -4,6 +4,7 @@
//Define the board type in makefile //Define the board type in makefile
//#define AVR_KAZZO //#define AVR_KAZZO
//#define STM_ADAPTER //#define STM_ADAPTER
//#define STM_INL6_PROTO
//#define STM_INL6 //#define STM_INL6
#ifdef AVR_CORE #ifdef AVR_CORE
@ -213,6 +214,89 @@ void software_AXL_CLK();
// Unlike all previous version above this has direct access to most pins // Unlike all previous version above this has direct access to most pins
// Only exception is one Flipflop for SegaGen A17-18, 20-23, #LO_MEM, & #TIME // Only exception is one Flipflop for SegaGen A17-18, 20-23, #LO_MEM, & #TIME
// flipflop also drives SNES PA0-7 // flipflop also drives SNES PA0-7
//
// This version had 16bit data bus mapped to PB2-15 & PA9-10 (D0-15 linearly)
// for 5v tolerance. This kept the data bits linear, but doesn't have
// much benefit and comes at the cost of slowing all 8bit data transfers.
// The final version below changed this mapping.
//
// PA8: NES connected to M2 & 21.4Mhz SYSTEM CLOCK
// SNES connected to both SYSCLK & MASTER CLOCK
// PA10: NES- CIRAM_CE
// PB1: NES CIC CLK & LED, this caused problems when SWIM needed to be on CICCLK
// SNES PA0-7 are behind flipflop, some of other expansion pins are SW alt signals or shared
// PA4: AUDIOL is connected to NES/famicom audio out which may conflict with GB pin31 irq/audio
//
//
// STM32F070RBT6 "INL RETRO 6" First Release
// minor changes to prototype above still has 6 connectors:
// GBA/DMG, SNES/SFC, NES, N64, Sega gen, Famicom
// Orange solder mask
// Labeled "INL RETRO PROGRAMMER DUMPER V2.0"
// Dated APR 2018
// Like prototype this has direct access to most pins but some are behind a flipflop
// It changed pinouts to gain connection to *ALL* cartridge pins unlike the prototype
// This version also added P-mos transistor and schottky diode for software control
// of Gameboy/GBA supply voltage.
//
// PB8-15: DATA 0-7
// PB2-7 and PA9-10: DATA 8-15
//
// NES changes:
// Expansion port connections are affected by rearrangement of DATA PORT
// but the assignment of D# to EXP# are the same
// NES M2 & SYSTEM CLOCK split up & CIRAM /CE moved
// PA8: 21Mhz SYSCLK
// PA10: M2 (can now be driven independent of software with TIM1_CH3)
// PA13: CIRAM /CE
// CIC CLK moved off of LED signal since will be used for SWIM
// PC0: Drives both A0 & CIC CLK
// PB1: LED doesn't share any NES signals
//
// SNES changes:
// Expansion PA0-7 are no longer behind flipflop, connected to AD0-7 instead
// PA /RD, PA /WR, /REFRESH, & /WRAMSEL are now mapped to FLIPFLOP:4-7
// SYSCLK & MASTER CLOCK split up
// PA1: SYSCLK (pin 57)
// PA8: 21Mhz MASTER CLOCK
// PA7: unused to keep from conflicting with GB power sel
// PA13: connected to EXPAND now
// PC0: Drives both A0 & CIC CLK
//
// SEGA GENESIS changes:
// PC0: AD0 is connected to A1 & #CAS
// PC1: AD1 is connected to A2 & Vsync
// PC2: AD2 is connected to A3 & Video
// PB1: LED is connected to #H_RESET (bidirectional hard reset should be open drain)
//
//
// GAMEBOY/GBA changes:
// pin31 GBirq/GBAaudio PA5 (AUDIOR) because NES/famicom may drive PA4 (audioL)
// PA7: selects GB voltage supply via Pmos & diode
// mcu pin connects to pmos gate with source connected to 5v
// schottky diode between 3v3 and GB power
// -PA7 low: Vgs = -5v, mosfet on, GB power ~5v
// -PA7 high: Vgs = -1.7v mosfet mostly off
// diode supplies power ~3v
// without a load on the GB slot, ~5v is present regardless of PA7
// BSS84 mosfet has max Id of 130mA with Rds of ~10ohm
// can support up to 520mA pulsed
// RB521S30T schottky diode has Vf of 0.5v @ 200mA
// @ 25C 20ma: Vf= 0.3v, 100mA: Vf= 0.37v
// testing data 47ohm load:
// PA7 low (0v @ gate) 90mA 4.74v (~2.8Rds plus fuse cable etc)
// PA7 hi (3.3v @ gate) 54mA 2.97v (~0.33Vf)
// testing data 23ohm load:
// PA7 low (0v @ gate) 159mA 4.51v (~2.8Rds plus fuse cable etc)
// Vusb = 4.84, Vfuse = 4.77, -> Vds = 260mV -> Rds = 1.6ohm
// PA7 hi (3.3v @ gate) 103mA 2.94v (~0.36Vf)
// in practice should be able to expect GB power to be 2.9v / 4.5v
// this more than satisfies 2.7v requirement for 3v flash
// and 4.5v is more than adequate for 5v chips/regulators
//
//
//
//
@ -368,12 +452,32 @@ void software_AXL_CLK();
// //
// --------------------------------------------------------------------------------------- // ---------------------------------------------------------------------------------------
#ifdef STM_INL6 #ifdef STM_INL6_PROTO
// PC0 "MCO" mcupinA8 // PC0 "M2" mcupinA8
#define C0bank GPIOA #define C0bank GPIOA
#define C0 (8U) #define C0 (8U)
// PC6 "CICE" mcupinA10
#define C6bank GPIOA
#define C6 (10U)
#endif
#ifdef STM_INL6
// PC0 "M2" mcupinA10
#define C0bank GPIOA
#define C0 (10U)
// PC6 "CICE" mcupinA13
#define C6bank GPIOA
#define C6 (13U)
#endif
#if defined (STM_INL6_PROTO) || defined(STM_INL6)
// PC1 "ROMSEL" mcupinA0 // PC1 "ROMSEL" mcupinA0
#define C1bank GPIOA #define C1bank GPIOA
#define C1 (0U) #define C1 (0U)
@ -394,10 +498,6 @@ void software_AXL_CLK();
#define C5bank GPIOA #define C5bank GPIOA
#define C5 (3U) #define C5 (3U)
// PC6 "CICE" mcupinA10
#define C6bank GPIOA
#define C6 (10U)
// PC7 "AHL" // PC7 "AHL"
// Not defined // Not defined
#define C7nodef #define C7nodef
@ -434,7 +534,7 @@ void software_AXL_CLK();
#define C15bank GPIOA #define C15bank GPIOA
#define C15 (5U) #define C15 (5U)
// PC16 "CIN" mcupinA7 // PC16 "GBP" mcupinA7
#define C16bank GPIOA #define C16bank GPIOA
#define C16 (7U) #define C16 (7U)
@ -459,6 +559,7 @@ void software_AXL_CLK();
#define C21 C15 #define C21 C15
/* NEED MORE UNIQUE names for these pins to not conflict with Data port definitions... /* NEED MORE UNIQUE names for these pins to not conflict with Data port definitions...
* these changed around from proto to final
// PCxx "D8" mcupinB10 // PCxx "D8" mcupinB10
#define Cxxbank GPIOB #define Cxxbank GPIOB
#define Cxx (10U) #define Cxx (10U)
@ -492,11 +593,11 @@ void software_AXL_CLK();
#define RCC_AHBENR_EXP (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN) #define RCC_AHBENR_EXP (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN)
#endif //STM_INL6 #endif //STM_INL6 & PROTO
#ifdef STM_ADAPTER #ifdef STM_ADAPTER
// PC0 "MCO" mcupinA3 // PC0 "M2" mcupinA3
#define C0bank GPIOA #define C0bank GPIOA
#define C0 (3U) #define C0 (3U)
@ -563,7 +664,7 @@ void software_AXL_CLK();
// Not defined // Not defined
#define C15nodef #define C15nodef
// PC16 "CIN" // PC16 "GBP"
// Not defined // Not defined
#define C16nodef #define C16nodef
@ -597,7 +698,7 @@ void software_AXL_CLK();
#ifdef AVR_KAZZO #ifdef AVR_KAZZO
// PC0 "MCO" mcupinC0 // PC0 "M2" mcupinC0
#define C0bank GPIOC #define C0bank GPIOC
#define C0 (0U) #define C0 (0U)
@ -664,7 +765,7 @@ void software_AXL_CLK();
// not defined // not defined
#define C15nodef #define C15nodef
// PC16 "CIN" // PC16 "GBP"
// not defined // not defined
#define C16nodef #define C16nodef
@ -697,9 +798,9 @@ void software_AXL_CLK();
//////////////////////////////////////////////////////////////////////////////// ////////////////////////////////////////////////////////////////////////////////
// //
// PC0-13 are defined based on majority of avr kazzos PORTC-PORTD // PC0-13 are defined based on majority of avr kazzos PORTC-PORTD
// PC0 "MCO" mcu clock out M2/phi2, Sysclk, etc // PC0 "M2" NES M2/phi2
#define MCO C0 #define M2 C0
#define MCObank C0bank #define M2bank C0bank
// PC1 "ROMSEL" Cartridge rom enable // PC1 "ROMSEL" Cartridge rom enable
#define ROMSEL C1 #define ROMSEL C1
@ -733,7 +834,7 @@ void software_AXL_CLK();
#define EXP0 C8 #define EXP0 C8
#define EXP0bank C8bank #define EXP0bank C8bank
// PC9 "LED" kazzos tied this to NES EXP9, INL6 connects to CIC CLK // PC9 "LED" kazzos tied this to NES EXP9
#define LED C9 #define LED C9
#define LEDbank C9bank #define LEDbank C9bank
@ -762,9 +863,9 @@ void software_AXL_CLK();
#define AUDR C15 #define AUDR C15
#define AUDRbank C15bank #define AUDRbank C15bank
// PC16 "CIN" CIC data in // PC16 "GBP" Gameboy power select
#define CIN C16 #define GBP C16
#define CINbank C16bank #define GBPbank C16bank
// PC17 "SWD" mcu debug // PC17 "SWD" mcu debug
#define SWD C17 #define SWD C17
@ -853,7 +954,8 @@ void software_AXL_CLK();
// CONTROL PORT MACROS to simplify flipflop operations // CONTROL PORT MACROS to simplify flipflop operations
// //
#ifndef STM_INL6 //#ifndef STM_INL6
#if !defined (STM_INL6_PROTO) && !defined(STM_INL6)
#ifdef GREEN_KAZZO #ifdef GREEN_KAZZO
#define AHL_CLK() software_AHL_CLK() #define AHL_CLK() software_AHL_CLK()
@ -884,13 +986,34 @@ void software_AXL_CLK();
// //
#ifdef STM_INL6 #ifdef STM_INL6
//All 8bits are on upper byte of GPIOB inorder
//PB8-15 map to D0-7
//PB2-7 map to D8-13
//PA9-10 map to D14-15 (unchanged from prototype)
#define Dbank GPIOB
//IP and OP assume MODER[1] is clear (ie not set to Alt Func)
//also assume PUPDR is reset default floating
#define DATA_IP_PU() Dbank->MODER &= ~(MODER_OP_ALL & 0xFFFF0000); Dbank->PUPDR |= (PUPDR_PU_ALL & 0xFFFF0000)
#define DATA_IP() Dbank->MODER &= ~(MODER_OP_ALL & 0xFFFF0000)
#define DATA_OP() Dbank->MODER |= (MODER_OP_ALL & 0xFFFF0000)
#define DATA_SET(data) Dbank->ODR = (Dbank->ODR & 0x00FF) | (data<<8)
#define DATA_RD(data) data = (Dbank->IDR>>8) & 0x00FF
#define DATA_EN_CLK() RCC->AHBENR |= RCC_AHBENR_DATA
#define DATA_ENABLE() DATA_EN_CLK(); DATA_IP_PU();
#endif //STM_INL6
#ifdef STM_INL6_PROTO
//All 8bits are on GPIOB inorder, but mapped to bits9-2 for 5v tolerance //All 8bits are on GPIOB inorder, but mapped to bits9-2 for 5v tolerance
//I get why I designed it that way so D8-13 could follow in order.. //I get why I designed it that way so D8-13 could follow in order..
//But with D8-15 required to be broken up anyways, perhaps it would have //But with D8-15 required to be broken up anyways, perhaps it would have
//made more sense to map D0-7 to bits 9-15 so byte access could be performed //made more sense to map D0-7 to bits 9-15 so byte access could be performed
//without shifting on Data7-0... //without shifting on Data7-0...
//IDK if I will reroute the board for production or not... Only other way to //This is what I did for final production version v2.0 above
//do it senisbly really makes a mess of the upper byte of Data
#define Dbank GPIOB #define Dbank GPIOB
//IP and OP assume MODER[1] is clear (ie not set to Alt Func) //IP and OP assume MODER[1] is clear (ie not set to Alt Func)
@ -905,7 +1028,7 @@ void software_AXL_CLK();
#define DATA_ENABLE() DATA_EN_CLK(); DATA_IP_PU(); #define DATA_ENABLE() DATA_EN_CLK(); DATA_IP_PU();
#endif //STM_INL6 #endif //STM_INL6_PROTO
#ifdef STM_ADAPTER #ifdef STM_ADAPTER
@ -953,7 +1076,7 @@ void software_AXL_CLK();
// //
// --------------------------------------------------------------------------------------- // ---------------------------------------------------------------------------------------
#ifdef STM_INL6 #if defined (STM_INL6_PROTO) || defined(STM_INL6)
//All 16bits are on GPIOC in perfect alignment //All 16bits are on GPIOC in perfect alignment
#define Abank GPIOC #define Abank GPIOC
@ -963,12 +1086,17 @@ void software_AXL_CLK();
#define ADDR_OP() Abank->MODER |= MODER_OP_ALL #define ADDR_OP() Abank->MODER |= MODER_OP_ALL
#define ADDRL(low) Abank->ODR = (Abank->ODR & 0xFF00) | low #define ADDRL(low) Abank->ODR = (Abank->ODR & 0xFF00) | low
#define ADDRH(high) Abank->ODR = (Abank->ODR & 0x00FF) | (high<<8) #define ADDRH(high) Abank->ODR = (Abank->ODR & 0x00FF) | (high<<8)
//Not sure why but this wasn't working on inl6 detection of vertical mirroring was failing..
//seems to not be reading the ODR, maybe getting optimized out..?
//works fine on stmad and AVR which have ADDRH behind flipflop
//Appears to be working for setting A10, but not A11 reguardless of order of execution..
//TODO really these macros should be making byte writes to the registers, not 16bit RMW
#define ADDR_SET(hword) Abank->ODR = hword #define ADDR_SET(hword) Abank->ODR = hword
#define ADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_ADDR #define ADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_ADDR
#define ADDR_ENABLE() ADDR_EN_CLK(); ADDR_OP() #define ADDR_ENABLE() ADDR_EN_CLK(); ADDR_OP()
#endif //STM_INL6 #endif //STM_INL6 & PROTO
#ifdef STM_ADAPTER #ifdef STM_ADAPTER
@ -1036,7 +1164,7 @@ void software_AXL_CLK();
// //
// --------------------------------------------------------------------------------------- // ---------------------------------------------------------------------------------------
#ifdef STM_INL6 #if defined (STM_INL6_PROTO) || defined(STM_INL6)
//pins1-5 = GPIOB10-14 (D8-12), pin6 = GPIOA4 (AUDL), pin7 = GPIOB15 (D13), pin8 = GPIOA14 (SWCLK) //pins1-5 = GPIOB10-14 (D8-12), pin6 = GPIOA4 (AUDL), pin7 = GPIOB15 (D13), pin8 = GPIOA14 (SWCLK)
//these defines are quite the mess currently due to pins all over the place //these defines are quite the mess currently due to pins all over the place
@ -1056,7 +1184,7 @@ void software_AXL_CLK();
#define EXP_ENABLE() ADDR_EN_CLK(); EXP_OP() #define EXP_ENABLE() ADDR_EN_CLK(); EXP_OP()
#define EXP_DISABLE() EXP_PU(); EXP_IP() #define EXP_DISABLE() EXP_PU(); EXP_IP()
//end STM_INL6 //end STM_INL6 & PROTO
#else //AVR_KAZZO or STM_ADAPTER #else //AVR_KAZZO or STM_ADAPTER
@ -1097,16 +1225,16 @@ void software_AXL_CLK();
// //
// --------------------------------------------------------------------------------------- // ---------------------------------------------------------------------------------------
#ifdef STM_INL6 #if defined STM_INL6_PROTO
//A16-21 are on PB10-15 these also map to EXP1-5, & 7 //A16-21 are on PB10-15 these also map to EXP1-5, & 7
//A22-23 are on PA9-10 these also map to CIRAM A10 & CIRAM /CE respectively //A22-23 are on PA9-10 these also map to CIRAM A10 & CIRAM /CE respectively
#define A16_21bank GPIOB #define A16_21bank GPIOB
#define A22_23bank GPIOA #define A22_23bank GPIOA
#define HADDR_PU() A16_21bank->PUPDR |= (PUPDR_PU_ALL & 0xFFF00000); A22_23bank->PUPDR |= (PUPDR_PU_ALL & 0x0003C000) #define HADDR_PU() A16_21bank->PUPDR |= (PUPDR_PU_ALL & 0xFFF00000); A22_23bank->PUPDR |= (PUPDR_PU_ALL & 0x003C0000)
#define HADDR_IP() A16_21bank->MODER &=~(MODER_OP_ALL & 0xFFF00000); A22_23bank->MODER &=~(MODER_OP_ALL & 0x0003C000) #define HADDR_IP() A16_21bank->MODER &=~(MODER_OP_ALL & 0xFFF00000); A22_23bank->MODER &=~(MODER_OP_ALL & 0x003C0000)
#define HADDR_OP() A16_21bank->MODER |= (MODER_OP_ALL & 0xFFF00000); A22_23bank->MODER |= (MODER_OP_ALL & 0x0003C000) #define HADDR_OP() A16_21bank->MODER |= (MODER_OP_ALL & 0xFFF00000); A22_23bank->MODER |= (MODER_OP_ALL & 0x003C0000)
#define HADDR_SET(val) A16_21bank->ODR = ((A16_21bank->ODR&0x03FF) | (val<<10 & 0xFC00)); A22_23bank->ODR = ((A22_23bank->ODR & 0xF9FF) | (val<<3 & 0x0600)) #define HADDR_SET(val) A16_21bank->ODR = ((A16_21bank->ODR&0x03FF) | (val<<10 & 0xFC00)); A22_23bank->ODR = ((A22_23bank->ODR & 0xF9FF) | (val<<3 & 0x0600))
@ -1114,7 +1242,24 @@ void software_AXL_CLK();
#define HADDR_ENABLE() HADDR_EN_CLK(); HADDR_OP() #define HADDR_ENABLE() HADDR_EN_CLK(); HADDR_OP()
#define HADDR_DISABLE() HADDR_PU(); HADDR_IP() #define HADDR_DISABLE() HADDR_PU(); HADDR_IP()
//end STM_INL6 #elif defined STM_INL6
//A16-21 are on PB2-7 these also map to EXP1-5, & 7 (changed from prototype)
//A22-23 are on PA9-10 these also map to CIRAM A10 & CIRAM /CE respectively
#define A16_21bank GPIOB
#define A22_23bank GPIOA
#define HADDR_PU() A16_21bank->PUPDR |= (PUPDR_PU_ALL & 0x0000FFF0); A22_23bank->PUPDR |= (PUPDR_PU_ALL & 0x003C0000)
#define HADDR_IP() A16_21bank->MODER &=~(MODER_OP_ALL & 0x0000FFF0); A22_23bank->MODER &=~(MODER_OP_ALL & 0x003C0000)
#define HADDR_OP() A16_21bank->MODER |= (MODER_OP_ALL & 0x0000FFF0); A22_23bank->MODER |= (MODER_OP_ALL & 0x003C0000)
#define HADDR_SET(val) A16_21bank->ODR = ((A16_21bank->ODR&0xFF03) | (val<<2 & 0x00FC)); A22_23bank->ODR = ((A22_23bank->ODR & 0xF9FF) | (val<<3 & 0x0600))
#define HADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_HADDR
#define HADDR_ENABLE() HADDR_EN_CLK(); HADDR_OP()
#define HADDR_DISABLE() HADDR_PU(); HADDR_IP()
//end STM_INL6 & PROTO
#else //AVR_KAZZO or STM_ADAPTER #else //AVR_KAZZO or STM_ADAPTER
@ -1156,7 +1301,7 @@ void software_AXL_CLK();
// //
// --------------------------------------------------------------------------------------- // ---------------------------------------------------------------------------------------
#ifdef STM_INL6 #if defined (STM_INL6_PROTO) || defined(STM_INL6)
// PE0 "A0" mcupinC0 // PE0 "A0" mcupinC0
#define E0bank GPIOC #define E0bank GPIOC
@ -1179,7 +1324,7 @@ void software_AXL_CLK();
#define E4 (12U) #define E4 (12U)
#endif //STM_INL6 #endif //STM_INL6 & PROTO
#ifdef STM_ADAPTER #ifdef STM_ADAPTER
@ -1228,7 +1373,7 @@ void software_AXL_CLK();
#define D0bank E1bank #define D0bank E1bank
//JTAG pins for INL6 //JTAG pins for INL6
#ifdef STM_INL6 #if defined (STM_INL6_PROTO) || defined(STM_INL6)
//TDI //TDI
#define D8 E2 #define D8 E2

427
firmware/source/snes.c
View File

@ -75,6 +75,22 @@ uint8_t snes_rom_rd( uint16_t addr )
NOP(); //add third nop for some extra NOP(); //add third nop for some extra
NOP(); //one more can't hurt NOP(); //one more can't hurt
//might need to wait longer for some carts... //might need to wait longer for some carts...
//this was long enough for AVR
//SNES v2.0p needed 6 more NOPs compared to v3.x & v1.x
//seems like a crazy long time...
NOP(); //v2.0p gets prod & density ID correct with addition of this NOP
//not sure why manf ID and sector ID are so much slower on v2 board
NOP();
NOP(); //v2.0p gets most bits right after 3 NOPs
NOP();
NOP(); //more after 5 extra...
NOP(); //all after 6 extra..
//sounds like 1 AVR NOP needs to equal 2STM32
//AVR running at 16Mhz, STM32 running at 48Mhz (3x as fast)
NOP(); //4MB proto needed this to get manfID, sector still bad
NOP(); //all good on 4MB proto
NOP(); //swapped for OR gate and takes a little longer now..?
//latch data //latch data
DATA_RD(read); DATA_RD(read);
@ -229,414 +245,3 @@ uint8_t snes_rom_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint
} }
// /* Desc: Discrete board PRG-ROM only write, does not write to mapper
// * PRG-ROM /WE <- EXP0 w/PU
// * PRG-ROM /OE <- /ROMSEL
// * PRG-ROM /CE <- GND
// * PRG-ROM write: /WE & /CE low, /OE high
// * mapper '161 CLK <- /ROMSEL
// * mapper '161 /LOAD <- PRG R/W
// * mapper '161 /LOAD must be low on rising edge of CLK to latch data
// * This is a /WE controlled write. Address latched on falling edge,
// * and data latched on rising edge EXP0
// * Note:addrH bit7 has no effect (ends up on PPU /A13)
// * /ROMSEL, M2, & PRG R/W signals untouched
// * Pre: nes_init() setup of io pins
// * Post:data latched by PRG-ROM, mapper register unaffected
// * address left on bus
// * data left on bus, but pullup only
// * EXP0 left pulled up
// * Rtn: None
// */
// void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
// {
// ADDR_SET(addr);
//
// DATA_OP();
// DATA_SET(data);
//
// EXP0_OP(); //Tas = 0ns, Tah = 30ns
// EXP0_LO();
// EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
// //16Mhz avr clk = 62.5ns period guarantees timing reqts
// DATA_IP();
// }
//
// //
// // /* Desc:Emulate NES CPU Read as best possible
// // * decode A15 from addrH to set /ROMSEL as expected
// // * float EXP0
// // * toggle M2 as NES would
// // * insert some NOP's in to be slow like NES
// // * Note:not the fastest read operation
// // * Pre: nes_init() setup of io pins
// // * Post:address left on bus
// // * data bus left clear
// // * EXP0 left floating
// // * Rtn: Byte read from PRG-ROM at addrHL
// // */
// // uint8_t emulate_nes_cpu_rd( uint8_t addrH, uint8_t addrL )
// // {
// // uint8_t read; //return value
// //
// // //m2 should be low as it aids in disabling WRAM
// // //this is also m2 state at beginging of CPU cycle
// // //all these pins should already be in this state, but
// // //go ahead and setup just to be sure since we're trying
// // //to be as accurate as possible
// // _EXP0_FLT(); //this could have been left pulled up
// // _M2_LO(); //start of CPU cycle
// // _ROMSEL_HI(); //trails M2
// // _PRGRW_RD(); //happens just after M2
// //
// // //set address bus
// // ADDR_OUT = addrL;
// // _ADDRH_SET(addrH);
// //
// // //couple NOP's to wait a bit
// // NOP();
// // NOP();
// //
// // //set M2 and /ROMSEL
// // if( addrH >= 0x80 ) { //addressing cart rom space
// // _M2_HI();
// // _ROMSEL_LO(); //romsel trails M2 during CPU operations
// // } else {
// // _M2_HI();
// // }
// //
// // //couple more NOP's waiting for data
// // NOP();
// // NOP();
// // NOP();
// // NOP();
// // NOP();
// // NOP();
// //
// // //latch data
// // read = DATA_IN;
// //
// // //return bus to default
// // _M2_LO();
// // _ROMSEL_HI();
// //
// // return read;
// // }
// //
// /* Desc:NES CPU Read without being so slow
// * decode A15 from addrH to set /ROMSEL as expected
// * float EXP0
// * toggle M2 as NES would
// * Pre: nes_init() setup of io pins
// * Post:address left on bus
// * data bus left clear
// * EXP0 left floating
// * Rtn: Byte read from PRG-ROM at addrHL
// */
// uint8_t nes_cpu_rd( uint16_t addr )
// {
// uint8_t read; //return value
//
// //set address bus
// ADDR_SET(addr);
//
// //set M2 and /ROMSEL
// MCO_HI();
// if( addr >= 0x8000 ) { //addressing cart rom space
// ROMSEL_LO(); //romsel trails M2 during CPU operations
// }
//
// //couple more NOP's waiting for data
// //zero nop's returned previous databus value
// NOP(); //one nop got most of the bits right
// NOP(); //two nop got all the bits right
// NOP(); //add third nop for some extra
// NOP(); //one more can't hurt
// //might need to wait longer for some carts...
//
// //latch data
// DATA_RD(read);
//
// //return bus to default
// MCO_LO();
// ROMSEL_HI();
//
// return read;
// }
//
// /* Desc:NES CPU Write
// * Just as you would expect NES's CPU to perform
// * A15 decoded to enable /ROMSEL
// * This ends up as a M2 and/or /ROMSEL controlled write
// * Note:addrH bit7 has no effect (ends up on PPU /A13)
// * EXP0 floating
// * Pre: nes_init() setup of io pins
// * Post:data latched by anything listening on the bus
// * address left on bus
// * data left on bus, but pullup only
// * Rtn: None
// */
// void nes_cpu_wr( uint16_t addr, uint8_t data )
// {
// //Float EXP0 as it should be in NES
// EXP0_IP_FL();
//
// //need for whole function
// //_DATA_OP();
//
// //set addrL
// //ADDR_OUT = addrL;
// //latch addrH
// //DATA_OUT = addrH;
// //_AHL_CLK();
// ADDR_SET(addr);
//
// //PRG R/W LO
// PRGRW_LO();
//
// //put data on bus
// DATA_OP();
// DATA_SET(data);
//
// //set M2 and /ROMSEL
// MCO_HI();
// if( addr >= 0x8000 ) { //addressing cart rom space
// ROMSEL_LO(); //romsel trails M2 during CPU operations
// }
//
// //give some time
// NOP();
// NOP();
//
// //latch data to cart memory/mapper
// MCO_LO();
// ROMSEL_HI();
//
// //retore PRG R/W to default
// PRGRW_HI();
//
// //Free data bus
// DATA_IP();
// }
//
// /* Desc:NES PPU Read
// * decode A13 from addrH to set /A13 as expected
// * Pre: nes_init() setup of io pins
// * Post:address left on bus
// * data bus left clear
// * Rtn: Byte read from CHR-ROM/RAM at addrHL
// */
// uint8_t nes_ppu_rd( uint16_t addr )
// {
// uint8_t read; //return value
//
// //addr with PPU /A13
// if (addr < 0x2000) { //below $2000 A13 clear, /A13 set
// addr |= PPU_A13N_WORD;
// } //above PPU $1FFF, A13 set, /A13 clear
//
// ADDR_SET( addr );
//
// //set CHR /RD and /WR
// CSRD_LO();
//
// //couple more NOP's waiting for data
// //zero nop's returned previous databus value
// NOP(); //one nop got most of the bits right
// NOP(); //two nop got all the bits right
// NOP(); //add third nop for some extra
// NOP(); //one more can't hurt
// //might need to wait longer for some carts...
//
// //latch data
// DATA_RD(read);
//
// //return bus to default
// CSRD_HI();
//
// return read;
// }
//
// /* Desc:NES PPU Write
// * decode A13 from addrH to set /A13 as expected
// * flash: address clocked falling edge, data rising edge of /WE
// * Pre: nes_init() setup of io pins
// * Post:data written to addrHL
// * address left on bus
// * data bus left clear
// * Rtn: None
// */
//
// void nes_ppu_wr( uint16_t addr, uint8_t data )
// {
//
// //addr with PPU /A13
// if (addr < 0x2000) { //below $2000 A13 clear, /A13 set
// addr |= PPU_A13N_WORD;
// } //above PPU $1FFF, A13 set, /A13 clear
//
// ADDR_SET( addr );
//
// //put data on bus
// DATA_OP();
// DATA_SET(data);
//
// NOP();
//
// //set CHR /RD and /WR
// CSWR_LO();
//
// //might need to wait longer for some carts...
// NOP(); //one can't hurt
//
// //latch data to memory
// CSWR_HI();
//
// //clear data bus
// DATA_IP();
//
// }
//
//
// /* Desc:PPU CIRAM A10 NT arrangement sense
// * Toggle A11 and A10 and read back CIRAM A10
// * report back if vert/horiz/1scnA/1scnB
// * reports nesdev defined mirroring
// * does not report Nintendo's "Name Table Arrangement"
// * Pre: nes_init() setup of io pins
// * Post:address left on bus
// * Rtn: MIR_VERT, MIR_HORIZ, MIR_1SCNA, MIR_1SCNB
// * errors not really possible since all combinations
// * of CIRAM A10 level designate something valid
// */
// uint8_t ciram_a10_mirroring( void )
// {
// uint16_t readV, readH;
//
// //set A10, clear A11
// ADDRH(A10_BYTE);
// CIA10_RD(readV);
//
// //set A11, clear A10
// ADDRH(A11_BYTE);
// CIA10_RD(readH);
//
// //if CIRAM A10 was always low -> 1 screen A
// if ((readV==0) & (readH==0)) return MIR_1SCNA;
// //if CIRAM A10 was always hight -> 1screen B
// if ((readV!=0) & (readH!=0)) return MIR_1SCNB;
// //if CIRAM A10 toggled with A10 -> Vertical mirroring, horizontal arrangement
// if ((readV!=0) & (readH==0)) return MIR_VERT;
// //if CIRAM A10 toggled with A11 -> Horizontal mirroring, vertical arrangement
// if ((readV==0) & (readH!=0)) return MIR_HORZ;
//
// //shouldn't be here...
// return GEN_FAIL;
// }
//
// /* Desc:NES CPU Page Read with optional USB polling
// * decode A15 from addrH to set /ROMSEL as expected
// * float EXP0
// * toggle M2 as NES would
// * if poll is true calls usbdrv.h usbPoll fuction
// * this is needed to keep from timing out when double buffering usb data
// * Pre: nes_init() setup of io pins
// * num_bytes can't exceed 256B page boundary
// * Post:address left on bus
// * data bus left clear
// * EXP0 left floating
// * data buffer filled starting at first to last
// * Rtn: Index of last byte read
// */
// uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
// {
// uint8_t i;
//
// //set address bus
// ADDRH(addrH);
//
// //set M2 and /ROMSEL
// MCO_HI();
// if( addrH >= 0x80 ) { //addressing cart rom space
// ROMSEL_LO(); //romsel trails M2 during CPU operations
// }
//
// //set lower address bits
// ADDRL(first); //doing this prior to entry and right after latching
// //gives longest delay between address out and latching data
// for( i=0; i<=len; i++ ) {
// //testing shows that having this if statement doesn't affect overall dumping speed
// if ( poll == FALSE ) {
// NOP(); //couple more NOP's waiting for data
// NOP(); //one prob good enough considering the if/else
// } else {
// usbPoll(); //Call usbdrv.h usb polling while waiting for data
// }
// //latch data
// DATA_RD(data[i]);
// //set lower address bits
// //ADDRL(++first); THIS broke things, on stm adapter because macro expands it twice!
// first++;
// ADDRL(first);
// }
//
// //return bus to default
// MCO_LO();
// ROMSEL_HI();
//
// //return index of last byte read
// return i;
// }
//
// /* Desc:NES PPU Page Read with optional USB polling
// * decode A13 from addrH to set /A13 as expected
// * if poll is true calls usbdrv.h usbPoll fuction
// * this is needed to keep from timing out when double buffering usb data
// * Pre: nes_init() setup of io pins
// * num_bytes can't exceed 256B page boundary
// * Post:address left on bus
// * data bus left clear
// * data buffer filled starting at first for len number of bytes
// * Rtn: Index of last byte read
// */
// uint8_t nes_ppu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
// {
// uint8_t i;
//
// if (addrH < 0x20) { //below $2000 A13 clear, /A13 set
// //ADDRH(addrH | PPU_A13N_BYTE);
// //Don't do weird stuff like above! logic inside macro expansions can have weird effects!!
// addrH |= PPU_A13N_BYTE;
// ADDRH(addrH);
// } else { //above PPU $1FFF, A13 set, /A13 clear
// ADDRH(addrH);
// }
//
// //set CHR /RD and /WR
// CSRD_LO();
//
// //set lower address bits
// ADDRL(first); //doing this prior to entry and right after latching
// //gives longest delay between address out and latching data
//
// for( i=0; i<=len; i++ ) {
// //couple more NOP's waiting for data
// if ( poll == FALSE ) {
// NOP(); //one prob good enough considering the if/else
// NOP();
// } else {
// usbPoll();
// }
// //latch data
// DATA_RD(data[i]);
// //set lower address bits
// first ++;
// ADDRL(first);
// }
//
// //return bus to default
// CSRD_HI();
//
// //return index of last byte read
// return i;
// }

64
firmware/source_stm_only/stm_init.c
View File

@ -54,7 +54,11 @@ void HardFault_Handler(void)
//pick define based on xtal setup for init_clock and init_usb_clock functions //pick define based on xtal setup for init_clock and init_usb_clock functions
//#define NO_XTAL //#define NO_XTAL
#define XTAL_16Mhz #ifdef STM_INL6
#define XTAL_8Mhz
#else //kaz6 prototype & stm adapter have 16Mhz xtal
#define XTAL_16Mhz
#endif
void init_clock() void init_clock()
{ {
#ifdef NO_XTAL // setup PLL for HSI * 2 = 16Mhz and set SYSCLK to use it #ifdef NO_XTAL // setup PLL for HSI * 2 = 16Mhz and set SYSCLK to use it
@ -104,6 +108,63 @@ void init_clock()
#endif #endif
#ifdef XTAL_8Mhz
//Turn on HSE
/* (2) Enable the CSS
* Enable the HSE and set HSEBYP to use the internal clock
* Enable HSE */
RCC->CR |= (RCC_CR_CSSON | RCC_CR_HSEON); /* (2) */
/* (1) Check the flag HSE ready */
while ((RCC->CR & RCC_CR_HSERDY) == 0) /* (1) */
{ /*spin while waiting for HSE to be ready */ }
/* (3) Switch the system clock to HSE */
//at startup HSI is selected SW = 00
RCC->CFGR |= RCC_CFGR_SW_HSE;
//TODO poll RCC->CFGR SWS bits to ensure sysclk switched over
//Now the SYSCLK is running directly off the HSE 16Mhz xtal
/* (1) Test if PLL is used as System clock */
// if ((RCC->CFGR & RCC_CFGR_SWS) == RCC_CFGR_SWS_PLL) {
// RCC->CFGR &= (uint32_t) (~RCC_CFGR_SW); /* (2) Select HSI as system clock */
// while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) /* (3) Wait for HSI switched */
// { /* For robust implementation, add here time-out management */ }
// }
//
// RCC->CR &= (uint32_t)(~RCC_CR_PLLON);/* (4) Disable the PLL */
// while((RCC->CR & RCC_CR_PLLRDY) != 0) /* (5) Wait until PLLRDY is cleared */
// { /* For robust implementation, add here time-out management */ }
//Set PLL Source to HSE, the PLL must be off to do this
RCC->CFGR |= RCC_CFGR_PLLSRC_HSE_PREDIV; //by default HSE isn't divided
////Set PLL to 16 * 3 = 48Mhz for USB
////RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PLLMUL) | RCC_CFGR_PLLMUL3; /* PLLMUL set to *2 at reset) */
//RCC->CFGR |= RCC_CFGR_PLLMUL3; /* PLLMUL set to *2 at reset) */
//RCC->CR |= RCC_CR_PLLON; /* (7) Enable the PLL */
//while((RCC->CR & RCC_CR_PLLRDY) == 0) /* (8) Wait until PLLRDY is set */
//{ /* For robust implementation, add here time-out management */ }
//
//Set PLL to 8 * 6 = 48Mhz for USB
//RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_PLLMUL) | RCC_CFGR_PLLMUL3; /* PLLMUL set to *2 at reset) */
RCC->CFGR |= RCC_CFGR_PLLMUL6; /* PLLMUL set to *2 at reset) */
RCC->CR |= RCC_CR_PLLON; /* (7) Enable the PLL */
while((RCC->CR & RCC_CR_PLLRDY) == 0) /* (8) Wait until PLLRDY is set */
{ /* For robust implementation, add here time-out management */ }
//test SYSCLK with 48Mhz
// FLASH->ACR |= (uint32_t) 0x01; //If >24Mhz SYSCLK, must add wait state to flash
// RCC->CFGR = (RCC->CFGR & ~RCC_CFGR_SW) | RCC_CFGR_SW_PLL; /* (9) Select PLL as system clock */
// while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) /* (10) Wait until the PLL is switched on */
// { /* For robust implementation, add here time-out management */ }
#endif
#ifdef XTAL_16Mhz #ifdef XTAL_16Mhz
@ -165,5 +226,6 @@ void init_clock()
//AHB APB clock setup: //AHB APB clock setup:
//these are not divided by default //these are not divided by default
} }

2
host/Makefile
View File

@ -5,7 +5,7 @@ WINLIB= -L ./winlib
LIBUSB= -lusb-1.0 LIBUSB= -lusb-1.0
CC= gcc CC= gcc
SOURCES=$(wildcard source/*.c) SOURCES=$(wildcard source/*.c source/lua/*.c)
OBJECTS=$(patsubst %.c,%.o,$(SOURCES)) OBJECTS=$(patsubst %.c,%.o,$(SOURCES))
LUAOBJ=$(wildcard source/lua/*.o) LUAOBJ=$(wildcard source/lua/*.o)

BIN
host/inlretro.exe
View File

Binary file not shown.

3
host/scripts/app/flash.lua
View File

@ -534,7 +534,8 @@ local function flash_snes( file, debug )
--print(nak, "cur_buff->status: ", cur_buff_status) --print(nak, "cur_buff->status: ", cur_buff_status)
cur_buff_status = dict.buffer("GET_CUR_BUFF_STATUS") cur_buff_status = dict.buffer("GET_CUR_BUFF_STATUS")
end end
if ( i == 2048*1024/buff_size) then break end --if ( i == 2048*1024/buff_size) then break end
if ( i == 4096*1024/buff_size) then break end
-- if ( i == 32*1024/buff_size) then break end -- if ( i == 32*1024/buff_size) then break end
i = i + 1 i = i + 1
-- if ( (i % (2048*1024/buff_size/16)) == 0) then -- if ( (i % (2048*1024/buff_size/16)) == 0) then

8
host/scripts/app/nes.lua
View File

@ -133,7 +133,7 @@ local function detect_mapper_mirroring (debug)
local rv local rv
print("attempting to detect NES/FC mapper via mirroring..."); if(debug) then print("attempting to detect NES/FC mapper via mirroring...") end
-- //TODO call mmc3 detection function -- //TODO call mmc3 detection function
-- --
-- //TODO call mmc1 detection function -- //TODO call mmc1 detection function
@ -144,16 +144,20 @@ local function detect_mapper_mirroring (debug)
rv = dict.nes("CIRAM_A10_MIRROR") rv = dict.nes("CIRAM_A10_MIRROR")
if (rv == op_nes["MIR_VERT"]) then if (rv == op_nes["MIR_VERT"]) then
if debug then print("vertical mirroring sensed") end if debug then print("vertical mirroring sensed") end
return "VERT"
elseif rv == op_nes["MIR_HORZ"] then elseif rv == op_nes["MIR_HORZ"] then
if debug then print("horizontal mirroring sensed") end if debug then print("horizontal mirroring sensed") end
return "HORZ"
elseif rv == op_nes["MIR_1SCNA"] then elseif rv == op_nes["MIR_1SCNA"] then
if debug then print("1screen A mirroring sensed") end if debug then print("1screen A mirroring sensed") end
return "1SCNA"
elseif rv == op_nes["MIR_1SCNB"] then elseif rv == op_nes["MIR_1SCNB"] then
if debug then print("1screen B mirroring sensed") end if debug then print("1screen B mirroring sensed") end
return "1SCNB"
end end
-- Rtn: VERT/HORIZ/1SCNA/1SCNB -- Rtn: VERT/HORIZ/1SCNA/1SCNB
return true return nil
end end
-- Desc:CHR-ROM flash manf/prod ID sense test -- Desc:CHR-ROM flash manf/prod ID sense test

321
host/scripts/inlretro.lua
View File

@ -22,11 +22,18 @@ function main ()
--cart/mapper specific scripts --cart/mapper specific scripts
--local curcart = require "scripts.nes.nrom" --local curcart = require "scripts.nes.nrom"
--local curcart = require "scripts.nes.mmc1"
--local curcart = require "scripts.nes.unrom" --local curcart = require "scripts.nes.unrom"
local curcart = require "scripts.nes.bnrom" --local curcart = require "scripts.nes.mm2"
--local curcart = require "scripts.nes.mapper30"
--local curcart = require "scripts.nes.bnrom"
--local curcart = require "scripts.nes.cdream" --local curcart = require "scripts.nes.cdream"
--local curcart = require "scripts.nes.cninja"
--local curcart = require "scripts.nes.action53" --local curcart = require "scripts.nes.action53"
--local curcart = require "scripts.nes.action53_tsop" --local curcart = require "scripts.nes.action53_tsop"
--local curcart = require "scripts.nes.easyNSF"
--local curcart = require "scripts.nes.dualport"
local curcart = require "scripts.snes.v3"
local rv local rv
-- rv = dict.pinport( "DATA_SET", 0xAA ) -- rv = dict.pinport( "DATA_SET", 0xAA )
@ -71,7 +78,7 @@ function main ()
--PROCESS USER ARGS ON WHAT IS TO BE DONE WITH CART --PROCESS USER ARGS ON WHAT IS TO BE DONE WITH CART
local force_cart = true local force_cart = true
cart_console = "NES" cart_console = "SNES"
if (force_cart or cart.detect_console(true)) then if (force_cart or cart.detect_console(true)) then
if cart_console == "NES" or cart_console == "Famicom" then if cart_console == "NES" or cart_console == "Famicom" then
@ -152,7 +159,7 @@ function main ()
--]] --]]
---[[ --[[
--test reading back CIC version --test reading back CIC version
dict.io("SWIM_INIT", "SWIM_ON_A0") dict.io("SWIM_INIT", "SWIM_ON_A0")
if swim.start(true) then if swim.start(true) then
@ -176,19 +183,49 @@ function main ()
--NROM --NROM
--curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/ddug2.bin", "ignore/verifyout.bin") --curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/ddug2.bin", "ignore/verifyout.bin")
--DUALPORT
--curcart.process( true, false, false, false, false, "ignore/dump.bin", "ignore/ddug2.bin", "ignore/verifyout.bin")
--MMC1
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/BB_sgrom.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/Zelda2.bin", "ignore/verifyout.bin")
--UxROM --UxROM
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/nomolosFINAL.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/nomolosFINAL.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/owlia_revb.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/owlia_revb.prg", "ignore/verifyout.bin")
--curcart.process( true, false, false, false, false, "ignore/dump.bin", "ignore/rushnattack.prg", "ignore/verifyout.bin")
--curcart.process( true, false, false, false, false, "ignore/dump.bin", "ignore/TDfix.prg", "ignore/verifyout.bin")
--MM2
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/mm2_i0.prg", "ignore/verifyout.bin")
--curcart.process( true, true, false, false, false, "ignore/dump.bin", "ignore/mm2_i0.prg", "ignore/verifyout.bin")
--UNROM512 mapper 30
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/MysticOrigins.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/tb_map30.prg", "ignore/verifyout.bin")
--BNROM --BNROM
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/lizard_v2.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/lizard_PG.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/lizard_v2_fr.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/lizard_v2_fr.prg", "ignore/verifyout.bin")
curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/hh85.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/hh85.prg", "ignore/verifyout.bin")
--COLOR DREAMS --COLOR DREAMS
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/multicart_mojontalesFINAL.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/multicart_mojontalesFINAL.prg", "ignore/verifyout.bin")
--COLOR NINJA
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/ninja.bin", "ignore/verifyout.bin")
--A53 PLCC --A53 PLCC
--curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/da53v2.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/a53v1_SBR2.prg", "ignore/verifyout.bin")
--A53 tssop --A53 tssop
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/a53vol3.prg", "ignore/verifyout.bin") --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/a53vol3.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/2a03puritans_RE.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/a53vol3_giftmsg_0xFF.prg", "ignore/verifyout.bin")
--curcart.process( true, false, false, false, false, "ignore/dump.bin", "ignore/writethe actual message.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/mappertests/test28-8Mbit.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/mappertests/M28_P1M_CR32K.prg", "ignore/verifyout.bin")
--easy NSF tssop
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/2a03puritans_RE.prg", "ignore/verifyout.bin")
--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/rndm2_1MB.prg", "ignore/verifyout.bin")
--[[ --[[
@ -223,132 +260,160 @@ function main ()
elseif cart_console == "SNES" then elseif cart_console == "SNES" then
snes_swimcart = nil --new SNES code
--[[
if swim.start(true) then
--SWIM is now established and running at HIGH SPEED
snes_swimcart = false --don't want to use SWIM pin to control flash /OE, use SNES RESET (EXP0) instead
--check if ROP set, allow clearing ROP and erasing CIC --SNES
--blindly erase STM8 CIC for now by disabling ROP --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/MMXdump.bin", "ignore/verifyout.bin")
swim.disable_ROP_erase(true) --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/smw.sfc", "ignore/verifyout.bin")
--curcart.process( true, true, false, false, false, "ignore/dump.bin", "ignore/hsbm_4Mbit_Lo.sfc", "ignore/verifyout.bin")
--open CIC file curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/hsbm_4Mbit_Lo.sfc", "ignore/verifyout.bin")
local cic_file = assert(io.open("SNESCIC_flashmode.bin", "rb")) --curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/hsbm_4Mbit_Hi.sfc", "ignore/verifyout.bin")
--write CIC file
swim.write_flash( cic_file )
--close CIC file
assert(cic_file:close())
-- reset STM8 CIC and end SWIM comms to it can execute what we just flashed
swim.stop_and_reset()
else
print("ERROR problem with STM8 CIC")
end
--]]
dict.io("IO_RESET")
dict.io("SNES_INIT")
--SNES detect HiROM or LoROM -- --old SNES code
--nes.detect_mapper_mirroring(true) --
local snes_mapping = "LOROM" -- snes_swimcart = nil
--SNES detect if there's save ram and size -- dict.io("IO_RESET")
-- print("start swim")
---[[ --
--SNES detect if able to read flash ID's -- dict.io("SWIM_INIT", "SWIM_ON_A0")
if not snes.read_flashID(true) then -- --[[
print("ERROR unable to read flash ID") -- if swim.start(true) then
return -- --SWIM is now established and running at HIGH SPEED
end -- snes_swimcart = false --don't want to use SWIM pin to control flash /OE, use SNES RESET (EXP0) instead
-- print("swim prgm mode")
--quick lame check to see if chip erased --
if snes.read_reset_vector(0, true) ~= 0xFFFF then -- --check if ROP set, allow clearing ROP and erasing CIC
erase.erase_snes( false ) -- --blindly erase STM8 CIC for now by disabling ROP
end -- swim.disable_ROP_erase(true)
if snes.read_reset_vector( 1, true) ~= 0xFFFF then --
erase.erase_snes( false ) -- --open CIC file
end -- local cic_file = assert(io.open("SNESCIC_flashmode.bin", "rb"))
if snes.read_reset_vector( 20, true) ~= 0xFFFF then --
erase.erase_snes( false ) -- --write CIC file
end -- swim.write_flash( cic_file )
if snes.read_reset_vector( 63, true) ~= 0xFFFF then --
erase.erase_snes( false ) -- --close CIC file
end -- assert(cic_file:close())
--
--FLASHING: -- -- reset STM8 CIC and end SWIM comms to it can execute what we just flashed
--erase cart -- swim.stop_and_reset()
-- else
-- print("ERROR problem with STM8 CIC")
-- end
-- --]]
--
-- dict.io("IO_RESET")
-- dict.io("SNES_INIT")
--
--
-- --SNES detect HiROM or LoROM
-- --nes.detect_mapper_mirroring(true)
-- local snes_mapping = "LOROM"
-- --SNES detect if there's save ram and size
--
-- ---[[
-- --SNES detect if able to read flash ID's
-- if not snes.read_flashID(true) then
-- print("ERROR unable to read flash ID")
-- return
-- end
--
-- erase.erase_snes( false ) -- erase.erase_snes( false )
--open file -- --quick lame check to see if chip erased
local file -- ---[[
---[[ file = assert(io.open("flash.bin", "rb")) -- if snes.read_reset_vector(0, true) ~= 0xFFFF then
--file = assert(io.open("SF2_PTdump_capcomFINAL.bin", "rb")) -- erase.erase_snes( false )
file = assert(io.open("ignore/MMXdump.bin", "rb")) -- end
-- if snes.read_reset_vector( 1, true) ~= 0xFFFF then
--calculate checksum -- erase.erase_snes( false )
--local data = file:read("*all") -- end
--print(crc32.hash(data)) -- if snes.read_reset_vector( 20, true) ~= 0xFFFF then
-- erase.erase_snes( false )
--determine if auto-doubling, deinterleaving, etc, -- end
--needs done to make board compatible with rom -- if snes.read_reset_vector( 63, true) ~= 0xFFFF then
--flash cart -- erase.erase_snes( false )
flash.flash_snes( file, true ) -- end
--close file -- --]]
assert(file:close()) --
--]] -- --FLASHING:
-- --erase cart
dict.io("IO_RESET") ---- erase.erase_snes( false )
print("start swim") -- --open file
-- local file
dict.io("SWIM_INIT", "SWIM_ON_A0") -- ---[[ file = assert(io.open("flash.bin", "rb"))
--flash final CIC code -- --file = assert(io.open("SF2_PTdump_capcomFINAL.bin", "rb"))
if swim.start(true) then -- file = assert(io.open("ignore/MMXdump.bin", "rb"))
--SWIM is now established and running at HIGH SPEED --
--swim.printCSR() -- --calculate checksum
--snes_swimcart = false -- --local data = file:read("*all")
--print("main swimcart", snes_swimcart) -- --print(crc32.hash(data))
--
swim.swim_test() -- --determine if auto-doubling, deinterleaving, etc,
-- --needs done to make board compatible with rom
--check if ROP set, allow clearing ROP and erasing CIC -- --flash cart
--blindly erase STM8 CIC for now by disabling ROP -- flash.flash_snes( file, true )
-- swim.disable_ROP_erase(true) -- --close file
-- assert(file:close())
--open CIC file -- --]]
local cic_file = assert(io.open("SNESCIC.bin", "rb")) --
-- dict.io("IO_RESET")
--write CIC file -- dict.io("SNES_INIT")
swim.write_flash( cic_file ) -- print("start swim")
--
--close CIC file -- --[[
assert(cic_file:close()) -- dict.io("SWIM_INIT", "SWIM_ON_A0")
-- --flash final CIC code
--write option bytes -- if swim.start(true) then
-- enable ROP, debug -- --SWIM is now established and running at HIGH SPEED
swim.write_optn_bytes( false, true ) -- --swim.printCSR()
-- --snes_swimcart = false
-- reset STM8 CIC and end SWIM comms to it can execute what we just flashed -- --print("main swimcart", snes_swimcart)
swim.stop_and_reset() --
else -- print("swimming")
print("ERROR problem with STM8 CIC") -- swim.swim_test()
end --
--]] -- --check if ROP set, allow clearing ROP and erasing CIC
-- --blindly erase STM8 CIC for now by disabling ROP
--DUMPING: -- -- swim.disable_ROP_erase(true)
--create new file --
print("dumping SNES") -- --open CIC file
snes.read_reset_vector(0, true) -- local cic_file = assert(io.open("SNESCIC.bin", "rb"))
local file --
file = assert(io.open("snesdump.bin", "wb")) -- --write CIC file
--dump cart into file ---- swim.write_flash( cic_file )
-- swim.start() --
-- dump.dump_snes( file, snes_mapping, true ) -- --close CIC file
-- assert(cic_file:close())
--close file --
assert(file:close()) -- --write option bytes
-- -- enable ROP, debug
---- swim.write_optn_bytes( false, true )
--
-- --read stack
-- swim.read_stack(true)
--
-- -- reset STM8 CIC and end SWIM comms to it can execute what we just flashed
-- swim.stop_and_reset()
--
-- else
-- print("ERROR problem with STM8 CIC")
-- end
-- --]]
--
--
-- --DUMPING:
-- --create new file
-- print("dumping SNES")
-- snes.read_reset_vector(0, true)
-- local file
-- file = assert(io.open("snesdump.bin", "wb"))
-- --dump cart into file
-- -- swim.start()
-- dump.dump_snes( file, snes_mapping, true )
--
-- --close file
-- assert(file:close())
--trick to do this at end while debugging so don't have to wait for it before starting --trick to do this at end while debugging so don't have to wait for it before starting

138
host/scripts/nes/action53_tsop.lua
View File

@ -47,6 +47,7 @@ local function init_mapper( debug )
--enable flash writes $5000 set to 0b0 101 010 0 --enable flash writes $5000 set to 0b0 101 010 0
dict.nes("NES_CPU_WR", 0x5000, 0x54) dict.nes("NES_CPU_WR", 0x5000, 0x54)
--dict.nes("NES_CPU_WR", 0x5555, 0x54)
end end
@ -54,6 +55,7 @@ end
--read PRG-ROM flash ID --read PRG-ROM flash ID
local function prgrom_manf_id( debug ) local function prgrom_manf_id( debug )
local rv
init_mapper() init_mapper()
if debug then print("reading PRG-ROM manf ID") end if debug then print("reading PRG-ROM manf ID") end
@ -66,10 +68,6 @@ local function prgrom_manf_id( debug )
if debug then print("attempted read PRG-ROM manf ID:", string.format("%X", rv)) end --0x01 if debug then print("attempted read PRG-ROM manf ID:", string.format("%X", rv)) end --0x01
rv = dict.nes("NES_CPU_RD", 0x8002) rv = dict.nes("NES_CPU_RD", 0x8002)
if debug then print("attempted read PRG-ROM prod ID:", string.format("%X", rv)) end --0xDA(top), 0x5B(bot) if debug then print("attempted read PRG-ROM prod ID:", string.format("%X", rv)) end --0xDA(top), 0x5B(bot)
-- rv = dict.nes("NES_CPU_RD", 0x801C)
-- if debug then print("attempted read PRG-ROM density ID:", string.format("%X", rv)) end
-- rv = dict.nes("NES_CPU_RD", 0x801E)
-- if debug then print("attempted read PRG-ROM bootsect ID:", string.format("%X", rv)) end
--exit software --exit software
dict.nes("NES_CPU_WR", 0x8000, 0xF0) dict.nes("NES_CPU_WR", 0x8000, 0xF0)
@ -77,6 +75,128 @@ local function prgrom_manf_id( debug )
end end
local function read_gift( base, len )
local rv
init_mapper()
--select last bank in read only mode
dict.nes("NES_CPU_WR", 0x5000, 0x81)
dict.nes("NES_CPU_WR", 0x8000, 0xFF)
local i = 0
while i < len do
rv = dict.nes("NES_CPU_RD", base+i)
io.write(string.char(rv))
i = i+1
end
i = 0
print("")
while i < len do
rv = dict.nes("NES_CPU_RD", base+i)
io.write(string.format("%X.", rv))
i = i+1
end
print("")
end
local function write_gift(base, off)
local i
local rv
init_mapper()
--select last bank in flash mode
dict.nes("NES_CPU_WR", 0x5000, 0x81)
dict.nes("NES_CPU_WR", 0x8000, 0xFF)
dict.nes("NES_CPU_WR", 0x5000, 0x54)
--enter unlock bypass mode
dict.nes("NES_CPU_WR", 0x8AAA, 0xAA)
dict.nes("NES_CPU_WR", 0x8555, 0x55)
dict.nes("NES_CPU_WR", 0x8AAA, 0x20)
--write 0xA0 to address of byte to write, then write data
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, 0x00) --end previous line
off=off+1
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, 0x15) --line number..?
off=off+1
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, string.byte("(",1)) --start with open parenth
--off = off + 1 --increase to start of message but index starting at 1
i = 1
--local msg1 = "Regular Edition"
--local msg1 = "Contributor Edition"
local msg1 = "Limited Edition"
local msg2 = "100 of 100" -- all flashed
--local msg1 = " Contributor Edition "
--local msg2 = " PinoBatch " --issue if capital P or R is first char for some reason..
local len = string.len(msg1)
while (i <= len) do
dict.nes("NES_CPU_WR", base+off+i, 0xA0)
dict.nes("NES_CPU_WR", base+off+i, string.byte(msg1,i)) --line 1 of message
print("write:", string.byte(msg1,i))
i=i+1
end
off = off + i
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, 0x00) --end current line
off=off+1
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, 0x16) --line number..?
off=off+1
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, string.byte("(",1)) --start with open parenth
i = 1
len = string.len(msg2)
while (i <= len) do
dict.nes("NES_CPU_WR", base+off+i, 0xA0)
dict.nes("NES_CPU_WR", base+off+i, string.byte(msg2,i)) --line 2 of message
print("write:", string.byte(msg2,i))
i=i+1
end
off = off + i
dict.nes("NES_CPU_WR", base+off, 0xA0)
dict.nes("NES_CPU_WR", base+off, 0x00) --end current line
--]]
--poll until stops toggling, or data is as wrote
-- rv = dict.nes("NES_CPU_RD", 0x8BDC)
-- print (rv)
--exit unlock bypass
dict.nes("NES_CPU_WR", 0x8000, 0x90)
dict.nes("NES_CPU_WR", 0x8000, 0x00)
--reset the flash chip
dict.nes("NES_CPU_WR", 0x8000, 0xF0)
end
--Cart should be in reset state upon calling this function --Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper --this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile) local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
@ -92,6 +212,16 @@ local function process( test, read, erase, program, verify, dumpfile, flashfile,
--test cart by reading manf/prod ID --test cart by reading manf/prod ID
if test then if test then
prgrom_manf_id(true) prgrom_manf_id(true)
--manipulate gift message
local base = 0x8BD0
local start_offset = 0xC
local len = 80
read_gift(base, len)
write_gift(base, start_offset)
read_gift(base, len)
end end
--dump the cart to dumpfile --dump the cart to dumpfile

26
host/scripts/nes/blank.lua Normal file
View File

@ -0,0 +1,26 @@
-- create the module's table
local blank = {}
-- import required modules
local dict = require "scripts.app.dict"
-- file constants
-- local functions
local function func()
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
blank.func = func
-- return the module's table
return blank

4
host/scripts/nes/bnrom.lua
View File

@ -136,9 +136,9 @@ local function process( test, read, erase, program, verify, dumpfile, flashfile,
--find bank table in the rom --find bank table in the rom
--write bank table to all banks of cartridge --write bank table to all banks of cartridge
--Lizard's bank table is at $FF94 so hard code that for now --Lizard's bank table is at $FF94 so hard code that for now
--wr_bank_table(0xFF94, 16) wr_bank_table(0xFF94, 16)
--hh85 bank table at $FFE0 --hh85 bank table at $FFE0
wr_bank_table(0xFFE0, 16) --wr_bank_table(0xFFE0, 16)
--flash cart --flash cart
flash.write_file( file, 512, "BxROM", "PRGROM", true ) flash.write_file( file, 512, "BxROM", "PRGROM", true )

236
host/scripts/nes/cdream.lua Normal file
View File

@ -0,0 +1,236 @@
-- create the module's table
local cdream = {}
-- import required modules
local dict = require "scripts.app.dict"
local nes = require "scripts.app.nes"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
-- file constants
-- local functions
local function wr_flash_byte(addr, value, debug)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xAA)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x2AAA, 0x55)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xA0)
dict.nes("DISCRETE_EXP0_PRGROM_WR", addr, value)
local rv = dict.nes("NES_CPU_RD", addr)
local i = 0
while ( rv ~= value ) do
rv = dict.nes("NES_CPU_RD", addr)
i = i + 1
end
if debug then print(i, "naks, done writing byte.") end
end
--base is the actual NES CPU address, not the rom offset (ie $FFF0, not $7FF0)
local function wr_bank_table(base, entries)
--CDREAMS needs to have a bank table present in each and every bank
--it should also be at the same location in every bank
--Perhaps it's possible to squeak by with only having it in the first bank as mojontales does..
--doesn't actually matter what bank this gets written to, lets ensure we can get to bank zero
wr_flash_byte(0x800C, 0x00)
--select first bank relying on 0 to override 1 for bus conflict
dict.nes("NES_CPU_WR", 0x800C, 0x00)
--write bank table to selected bank
local i = 0
while( i < entries) do
wr_flash_byte(base+i, i)
i = i+1;
end
--need a zero value in each bank to get back to first bank
wr_flash_byte(0x800C, 0x00) --first bank
--now place one in all the other banks
--first swap to next bank
i = 1
while( i < 16) do --16 banks total for 512KByte
dict.nes("NES_CPU_WR", 0x0000, 0x00) --select first bank
dict.nes("NES_CPU_WR", base+i, i) --jump to next bank
wr_flash_byte(0x800C, 0x00) --write zero byte
i = i + 1
end
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for NES
dict.io("IO_RESET")
dict.io("NES_INIT")
--test cart by reading manf/prod ID
if test then
nes.detect_mapper_mirroring(true)
print("EXP0 pull-up test:", dict.io("EXP0_PULLUP_TEST"))
nes.read_flashID_prgrom_exp0(true)
--enter software mode
--CDREAMS connects CHR-ROM A13-16 to mapper bits 4-8
--so need to set mapper register bits 4 & 5 properly to send unlock commands
--A13 needs to be low to address CHR-ROM
-- 15 14 13 12
-- 0x5 = 0b 0 1 0 1 -> bank:0x20 $1555
-- 0x2 = 0b 0 0 1 0 -> bank:0x10 $0AAA
--TODO find bank table prior to doing this
--or write to mapper without enabling PRG-ROM via exp0
--tried DISCRETE_EXP0_MAPPER_WR function but didn't work...
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_CPU_WR", 0x8000, 0x10)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0x90)
--read manf ID
rv = dict.nes("NES_PPU_RD", 0x0000)
if debug then print("attempted read CHR-ROM manf ID:", string.format("%X", rv)) end
--read prod ID
rv = dict.nes("NES_PPU_RD", 0x0001)
if debug then print("attempted read CHR-ROM prod ID:", string.format("%X", rv)) end
--exit software
dict.nes("NES_PPU_WR", 0x0000, 0xF0)
end
--dump the cart to dumpfile
if read then
file = assert(io.open(dumpfile, "wb"))
--TODO find bank table to avoid bus conflicts!
--dump cart into file
dump.dumptofile( file, 512, "CDREAM", "PRGROM", true )
dump.dumptofile( file, 128, "CDREAM", "CHRROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
print("\nerasing CDREAM");
print("erasing PRG-ROM");
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xAA)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x2AAA, 0x55)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0x80)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xAA)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x2AAA, 0x55)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0x10)
rv = dict.nes("NES_CPU_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_CPU_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing prg.");
print("erasing CHR-ROM");
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_CPU_WR", 0x8000, 0x10)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0x80)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_CPU_WR", 0x8000, 0x10)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0x10)
rv = dict.nes("NES_PPU_RD", 0x0000)
i = 0
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_PPU_RD", 0x0000)
i = i + 1
end
print(i, "naks, done erasing chr.\n");
end
--program flashfile to the cart
if program then
--open file
file = assert(io.open(flashfile, "rb"))
--determine if auto-doubling, deinterleaving, etc,
--needs done to make board compatible with rom
--find bank table in the rom
--write bank table to all banks of cartridge
--Mojontales bank table is at $CC43 so hard code that for now
wr_bank_table(0xCC43, 256)
--flash cart
-- flash.write_file( file, 32, "CDREAM", "PRGROM", true )
-- flash.write_file( file, 128, "CDREAM", "CHRROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
file = assert(io.open(verifyfile, "wb"))
--dump cart into file
dump.dumptofile( file, 512, "CDREAM", "PRGROM", true )
dump.dumptofile( file, 128, "CDREAM", "CHRROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
cdream.process = process
-- return the module's table
return cdream

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-- create the module's table
local cninja = {}
-- import required modules
local dict = require "scripts.app.dict"
local nes = require "scripts.app.nes"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
-- file constants
-- local functions
local function wr_flash_byte(addr, value, debug)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xAA)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x2AAA, 0x55)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xA0)
dict.nes("DISCRETE_EXP0_PRGROM_WR", addr, value)
local rv = dict.nes("NES_CPU_RD", addr)
local i = 0
while ( rv ~= value ) do
rv = dict.nes("NES_CPU_RD", addr)
i = i + 1
end
if debug then print(i, "naks, done writing byte.") end
end
--base is the actual NES CPU address, not the rom offset (ie $FFF0, not $7FF0)
local function wr_bank_table(base, entries)
--CNINJA needs to have a bank table present in each and every bank
--it should also be at the same location in every bank
--Perhaps it's possible to squeak by with only having it in the first bank as mojontales does..
--doesn't actually matter what bank this gets written to, lets ensure we can get to bank zero
wr_flash_byte(0x800C, 0x00)
--select first bank relying on 0 to override 1 for bus conflict
dict.nes("NES_CPU_WR", 0x800C, 0x00)
--write bank table to selected bank
local i = 0
while( i < entries) do
wr_flash_byte(base+i, i)
i = i+1;
end
--need a zero value in each bank to get back to first bank
wr_flash_byte(0x800C, 0x00) --first bank
--now place one in all the other banks
--first swap to next bank
i = 1
while( i < 16) do --16 banks total for 512KByte
dict.nes("NES_CPU_WR", 0x0000, 0x00) --select first bank
dict.nes("NES_CPU_WR", base+i, i) --jump to next bank
wr_flash_byte(0x800C, 0x00) --write zero byte
i = i + 1
end
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for NES
dict.io("IO_RESET")
dict.io("NES_INIT")
--test cart by reading manf/prod ID
if test then
nes.detect_mapper_mirroring(true)
print("EXP0 pull-up test:", dict.io("EXP0_PULLUP_TEST"))
-- doesn't work for cninja
--nes.read_flashID_prgrom_exp0(true)
--enter software mode
--CDREAMS connects CHR-ROM A13-16 to mapper bits 4-8
--so need to set mapper register bits 4 & 5 properly to send unlock commands
--A13 needs to be low to address CHR-ROM
-- 15 14 13 12
-- 0x5 = 0b 0 1 0 1 -> bank:0x20 $1555
-- 0x2 = 0b 0 0 1 0 -> bank:0x10 $0AAA
--TODO find bank table prior to doing this
--or write to mapper without enabling PRG-ROM via exp0
--tried DISCRETE_EXP0_MAPPER_WR function but didn't work...
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_CPU_WR", 0x8000, 0x10)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0x90)
--read manf ID
rv = dict.nes("NES_PPU_RD", 0x0000)
if debug then print("attempted read CHR-ROM manf ID:", string.format("%X", rv)) end
--read prod ID
rv = dict.nes("NES_PPU_RD", 0x0001)
if debug then print("attempted read CHR-ROM prod ID:", string.format("%X", rv)) end
--exit software
dict.nes("NES_PPU_WR", 0x0000, 0xF0)
--color ninja mapper has flash enable at $6000-7FFF which has to be 0xA5
-- dict.nes("NES_CPU_WR", 0x6000, 0xA5)
-- not actually needed to ID flash since 32KB banks
--now can write in flash mode
dict.nes("NES_CPU_WR", 0xD555, 0xAA)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xD555, 0x90)
rv = dict.nes("NES_CPU_RD", 0x8000)
if debug then print("attempted read PRG-ROM manf ID:", string.format("%X", rv)) end
--read prod ID
rv = dict.nes("NES_CPU_RD", 0x8001)
if debug then print("attempted read PRG-ROM prod ID:", string.format("%X", rv)) end
--exit software
dict.nes("NES_CPU_WR", 0x8000, 0xF0)
--exit flash mode
-- dict.nes("NES_CPU_WR", 0x6000, 0x00) --any value besides 0xA5
end
--dump the cart to dumpfile
if read then
file = assert(io.open(dumpfile, "wb"))
dict.nes("NES_CPU_WR", 0x6000, 0x00) --any value besides 0xA5
--TODO find bank table to avoid bus conflicts!
--dump cart into file
--dump.dumptofile( file, 128, "CNINJA", "PRGROM", true )
dump.dumptofile( file, 128, "CDREAM", "PRGROM", true )
dump.dumptofile( file, 128, "CDREAM", "CHRROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
print("\nerasing CNINJA");
print("erasing PRG-ROM");
--dict.nes("NES_CPU_WR", 0x6000, 0xA5)
dict.nes("NES_CPU_WR", 0xD555, 0xAA)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xD555, 0x80)
dict.nes("NES_CPU_WR", 0xD555, 0xAA)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xD555, 0x10)
rv = dict.nes("NES_CPU_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_CPU_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing prg.");
print("erasing CHR-ROM");
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_CPU_WR", 0x8000, 0x10)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0x80)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_CPU_WR", 0x8000, 0x10)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_CPU_WR", 0x8000, 0x20)
dict.nes("NES_PPU_WR", 0x1555, 0x10)
rv = dict.nes("NES_PPU_RD", 0x0000)
i = 0
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_PPU_RD", 0x0000)
i = i + 1
end
print(i, "naks, done erasing chr.\n");
end
--program flashfile to the cart
if program then
--open file
file = assert(io.open(flashfile, "rb"))
--determine if auto-doubling, deinterleaving, etc,
--needs done to make board compatible with rom
--no bank table due to no bus conflicts
--flash cart
dict.nes("NES_CPU_WR", 0x6000, 0xA5) --flash write enable
flash.write_file( file, 128, "CNINJA", "PRGROM", true )
dict.nes("NES_CPU_WR", 0x6000, 0x00) --any value besides 0xA5
flash.write_file( file, 128, "CDREAM", "CHRROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
file = assert(io.open(verifyfile, "wb"))
dict.nes("NES_CPU_WR", 0x6000, 0x00) --any value besides 0xAA
--TODO find bank table to avoid bus conflicts!
--dump cart into file
--dump.dumptofile( file, 128, "CNINJA", "PRGROM", true )
dump.dumptofile( file, 128, "CDREAM", "PRGROM", true )
dump.dumptofile( file, 128, "CDREAM", "CHRROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
cninja.process = process
-- return the module's table
return cninja

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-- create the module's table
local dualport = {}
-- import required modules
local dict = require "scripts.app.dict"
local nes = require "scripts.app.nes"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
-- file constants
-- local functions
local function init_mapper( debug )
--select bank 0 of flash
dict.nes("NES_PPU_WR", 0x3FFF, 0x00)
end
local function read_dp(addr)
dict.pinport("CTL_SET_HI", "M2")
-- dict.pinport("CTL_SET_LO", "ROMSEL")
dict.pinport("ADDR_SET", addr)
rv = dict.pinport("DATA_RD")
print( string.format("%X", rv))
--disable rom
--dict.pinport("CTL_SET_HI", "ROMSEL")
dict.pinport("CTL_SET_HI", "M2")
end
local function write_dp(addr, data)
--romsel controls /oe
-- dict.pinport("CTL_SET_HI", "ROMSEL")
--m2 controls /we
dict.pinport("CTL_SET_LO", "M2")
dict.pinport("ADDR_SET", addr)
dict.pinport("DATA_OP")
dict.pinport("DATA_SET", data)
--latch data
dict.pinport("CTL_SET_HI", "M2")
--leave data bus floating
dict.pinport("DATA_IP")
end
--read PRG-ROM flash ID
local function prgrom_manf_id( debug )
--SRAM TEST $2000-3FFF
--[[
dict.nes("NES_DUALPORT_WR", 0x2000, 0x00)
dict.nes("NES_DUALPORT_WR", 0x20AA, 0x00)
dict.nes("NES_DUALPORT_WR", 0x2055, 0x00)
dict.nes("NES_DUALPORT_WR", 0x3FFF, 0x00)
rv = dict.nes("NES_DUALPORT_RD", 0x2000)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x20AA)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x2055)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x3FFF)
print( string.format("%X", rv))
dict.nes("NES_DUALPORT_WR", 0x2000, 0x55)
dict.nes("NES_DUALPORT_WR", 0x20AA, 0x55)
dict.nes("NES_DUALPORT_WR", 0x2055, 0x55)
dict.nes("NES_DUALPORT_WR", 0x3FFF, 0x55)
rv = dict.nes("NES_DUALPORT_RD", 0x2000)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x20AA)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x2055)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x3FFF)
print( string.format("%X", rv))
dict.nes("NES_DUALPORT_WR", 0x2000, 0xDE)
dict.nes("NES_DUALPORT_WR", 0x20AA, 0xAD)
dict.nes("NES_DUALPORT_WR", 0x2055, 0xBE)
dict.nes("NES_DUALPORT_WR", 0x3FFF, 0xEF)
rv = dict.nes("NES_DUALPORT_RD", 0x2000)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x20AA)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x2055)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x3FFF)
print( string.format("%X", rv))
dict.nes("NES_DUALPORT_WR", 0x2000, 0x33)
dict.nes("NES_DUALPORT_WR", 0x3FFF, 0x33)
dict.nes("NES_DUALPORT_WR", 0x2555, 0x33)
dict.nes("NES_DUALPORT_WR", 0x3AAA, 0x33)
rv = dict.nes("NES_DUALPORT_RD", 0x2000)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x3FFF)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x2555)
print( string.format("%X", rv))
rv = dict.nes("NES_DUALPORT_RD", 0x3AAA)
print( string.format("%X", rv))
--]]
dict.nes("NES_DUALPORT_WR", 0x0AAA, 0xAA)
dict.nes("NES_DUALPORT_WR", 0x0555, 0x55)
dict.nes("NES_DUALPORT_WR", 0x0AAA, 0x90)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
if debug then print("attempted read DP PRG-ROM manf ID:", string.format("%X", rv)) end --0x01
rv = dict.nes("NES_DUALPORT_RD", 0x0002)
if debug then print("attempted read DP PRG-ROM prod ID:", string.format("%X", rv)) end --0xDA(top), 0x5B(bot)
--exit software mode
dict.nes("NES_DUALPORT_WR", 0x0000, 0x90)
end
--[[
local function wr_flash_byte(addr, value, debug)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xAA)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x2AAA, 0x55)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xA0)
dict.nes("DISCRETE_EXP0_PRGROM_WR", addr, value)
local rv = dict.nes("NES_CPU_RD", addr)
local i = 0
while ( rv ~= value ) do
rv = dict.nes("NES_CPU_RD", addr)
i = i + 1
end
if debug then print(i, "naks, done writing byte.") end
end
--]]
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for NES
dict.io("IO_RESET")
dict.io("NES_INIT")
--test cart by reading manf/prod ID
if test then
nes.detect_mapper_mirroring(true)
nes.ciramce_inv_ppuA13(true)
-- nes.ppu_ram_sense(0x1000, true)
-- print("EXP0 pull-up test:", dict.io("EXP0_PULLUP_TEST"))
--prgrom_manf_id( true )
rv = dict.nes("EMULATE_NES_CPU_RD", 0x8000)
print("read:", string.format("%X", rv))
rv = dict.nes("EMULATE_NES_CPU_RD", 0x8001)
print("read:", string.format("%X", rv))
rv = dict.nes("NES_CPU_RD", 0x8000)
print("read:", string.format("%X", rv))
rv = dict.nes("NES_CPU_RD", 0x8001)
print("read:", string.format("%X", rv))
rv = dict.nes("NES_PPU_RD", 0x0000)
print("read:", string.format("%X", rv))
rv = dict.nes("NES_PPU_RD", 0x0000)
print("read:", string.format("%X", rv))
--[[
--read some bytes to verify banking worked
dict.nes("NES_PPU_WR", 0x3FFF, 0x00)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
print("read:", string.format("%X", rv))
dict.nes("NES_PPU_WR", 0x3FFF, 0x01)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
print("read:", string.format("%X", rv))
dict.nes("NES_PPU_WR", 0x3FFF, 0x02)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
print("read:", string.format("%X", rv))
dict.nes("NES_PPU_WR", 0x3FFF, 0x03)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
print("read:", string.format("%X", rv))
dict.nes("NES_PPU_WR", 0x3FFF, 0x04)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
print("read:", string.format("%X", rv))
dict.nes("NES_PPU_WR", 0x3FFF, 0x05)
rv = dict.nes("NES_DUALPORT_RD", 0x0000)
print("read:", string.format("%X", rv))
--]]
end
--dump the cart to dumpfile
if read then
file = assert(io.open(dumpfile, "wb"))
--dump cart into file
dump.dumptofile( file, 64, "DPROM", "CHRROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
init_mapper()
print("\nerasing DUALPORT ROM");
--A0-A14 are all directly addressable in CNROM mode
--only A0-A11 are required to be valid for tsop-48
--and mapper writes don't affect PRG banking
dict.nes("NES_DUALPORT_WR", 0x8AAA, 0xAA)
dict.nes("NES_DUALPORT_WR", 0x8555, 0x55)
dict.nes("NES_DUALPORT_WR", 0x8AAA, 0x80)
dict.nes("NES_DUALPORT_WR", 0x8AAA, 0xAA)
dict.nes("NES_DUALPORT_WR", 0x8555, 0x55)
dict.nes("NES_DUALPORT_WR", 0x8AAA, 0x10)
rv = dict.nes("NES_DUALPORT_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_DUALPORT_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing flash");
end
--program flashfile to the cart
if program then
--open file
file = assert(io.open(flashfile, "rb"))
--flash cart
flash.write_file( file, 64, "DPROM", "CHRROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
file = assert(io.open(verifyfile, "wb"))
--dump cart into file
dump.dumptofile( file, 64, "DPROM", "CHRROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
dualport.process = process
-- return the module's table
return dualport

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-- create the module's table
local easyNSF = {}
-- import required modules
local dict = require "scripts.app.dict"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
-- file constants
-- local functions
--local function wr_flash_byte(addr, value, debug)
--base is the actual NES CPU address, not the rom offset (ie $FFF0, not $7FF0)
--local function wr_bank_table(base, entries)
--Action53 not susceptible to bus conflicts, no banktable needed
--initialize mapper for dump/flash routines
local function init_mapper( debug )
--rom A11-0 are directly connected to CPU
--A12 pin is part of sector address
--in BYTE mode, pin A12 is actually CPU A13
--so ROM A11 must be valid for flash commands
--ROM A11 pin is actually CPU A12
--A12 is actually controlled my mapper register...
--So it should need to be initialized to work, but flash ID is responding properly without it..
--Therefore I don't think rom A11 pin (CPU A12) needs to be valid, just A11-0?
dict.nes("NES_CPU_WR", 0x5000, 0x00)
dict.nes("NES_CPU_WR", 0x5001, 0x00)
dict.nes("NES_CPU_WR", 0x5002, 0x00)
dict.nes("NES_CPU_WR", 0x5003, 0x00)
dict.nes("NES_CPU_WR", 0x5004, 0x00)
dict.nes("NES_CPU_WR", 0x5005, 0x00)
dict.nes("NES_CPU_WR", 0x5006, 0x00)
dict.nes("NES_CPU_WR", 0x5007, 0x00)
end
--read PRG-ROM flash ID
local function prgrom_manf_id( debug )
local rv
init_mapper()
if debug then print("reading PRG-ROM manf ID") end
--A0-A14 are all directly addressable in CNROM mode
--and mapper writes don't affect PRG banking
dict.nes("NES_CPU_WR", 0x8AAA, 0xAA)
dict.nes("NES_CPU_WR", 0x8555, 0x55)
dict.nes("NES_CPU_WR", 0x8AAA, 0x90)
rv = dict.nes("NES_CPU_RD", 0x8000)
if debug then print("attempted read PRG-ROM manf ID:", string.format("%X", rv)) end --0x01
rv = dict.nes("NES_CPU_RD", 0x8002)
if debug then print("attempted read PRG-ROM prod ID:", string.format("%X", rv)) end --0xDA(top), 0x5B(bot)
--exit software
dict.nes("NES_CPU_WR", 0x8000, 0xF0)
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for NES
dict.io("IO_RESET")
dict.io("NES_INIT")
--test cart by reading manf/prod ID
if test then
prgrom_manf_id(true)
end
--dump the cart to dumpfile
if read then
--initialize the mapper for dumping
init_mapper(debug)
file = assert(io.open(dumpfile, "wb"))
--TODO find bank table to avoid bus conflicts!
--dump cart into file
dump.dumptofile( file, 1024, "EZNSF", "PRGROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
--initialize the mapper for erasing
init_mapper(debug)
print("\nerasing tsop takes ~30sec");
print("erasing PRG-ROM");
--A0-A14 are all directly addressable in CNROM mode
--only A0-A11 are required to be valid for tsop-48
--and mapper writes don't affect PRG banking
dict.nes("NES_CPU_WR", 0x8AAA, 0xAA)
dict.nes("NES_CPU_WR", 0x8555, 0x55)
dict.nes("NES_CPU_WR", 0x8AAA, 0x80)
dict.nes("NES_CPU_WR", 0x8AAA, 0xAA)
dict.nes("NES_CPU_WR", 0x8555, 0x55)
dict.nes("NES_CPU_WR", 0x8AAA, 0x10)
rv = dict.nes("NES_CPU_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_CPU_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing prg.");
end
--program flashfile to the cart
if program then
--initialize the mapper for dumping
init_mapper(debug)
--open file
file = assert(io.open(flashfile, "rb"))
--determine if auto-doubling, deinterleaving, etc,
--needs done to make board compatible with rom
--not susceptible to bus conflicts
--flash cart
flash.write_file( file, 1024, "EZNSF", "PRGROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
--initialize the mapper for dumping
init_mapper(debug)
file = assert(io.open(verifyfile, "wb"))
--dump cart into file
dump.dumptofile( file, 1024, "EZNSF", "PRGROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
easyNSF.process = process
-- return the module's table
return easyNSF

163
host/scripts/nes/mapper30.lua Normal file
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@ -0,0 +1,163 @@
-- create the module's table
local mapper30 = {}
-- import required modules
local dict = require "scripts.app.dict"
local nes = require "scripts.app.nes"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
-- file constants
-- local functions
--read PRG-ROM flash ID
local function prgrom_manf_id( debug )
if debug then print("reading PRG-ROM manf ID") end
--no bus conflicts
--$8000-BFFF writes to flash
--$C000-FFFF writes to mapper
--ROM A14 is mapper controlled
--
--A15 14 - 13 12
-- 1 1 0 1 : 0x5555 -> bank1, $9555
-- 1 0 1 0 : 0x2AAA -> bank0, $AAAA
dict.nes("NES_CPU_WR", 0xC000, 0x01)
dict.nes("NES_CPU_WR", 0x9555, 0xAA)
dict.nes("NES_CPU_WR", 0xC000, 0x00)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xC000, 0x01)
dict.nes("NES_CPU_WR", 0x9555, 0x90)
rv = dict.nes("NES_CPU_RD", 0x8000)
if debug then print("attempted read PRG-ROM manf ID:", string.format("%X", rv)) end
rv = dict.nes("NES_CPU_RD", 0x8001)
if debug then print("attempted read PRG-ROM prod ID:", string.format("%X", rv)) end
--exit software
dict.nes("NES_CPU_WR", 0x8000, 0xF0)
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for NES
dict.io("IO_RESET")
dict.io("NES_INIT")
--test cart by reading manf/prod ID
if test then
nes.detect_mapper_mirroring(true)
nes.ppu_ram_sense(0x1000, true)
print("EXP0 pull-up test:", dict.io("EXP0_PULLUP_TEST"))
prgrom_manf_id( debug )
end
--dump the cart to dumpfile
if read then
file = assert(io.open(dumpfile, "wb"))
--dump cart into file
dump.dumptofile( file, 512, "MAP30", "PRGROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
print("\nerasing mapper 30");
print("erasing PRG-ROM");
dict.nes("NES_CPU_WR", 0xC000, 0x01)
dict.nes("NES_CPU_WR", 0x9555, 0xAA)
dict.nes("NES_CPU_WR", 0xC000, 0x00)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xC000, 0x01)
dict.nes("NES_CPU_WR", 0x9555, 0x80)
dict.nes("NES_CPU_WR", 0xC000, 0x01)
dict.nes("NES_CPU_WR", 0x9555, 0xAA)
dict.nes("NES_CPU_WR", 0xC000, 0x00)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xC000, 0x01)
dict.nes("NES_CPU_WR", 0x9555, 0x10)
rv = dict.nes("NES_CPU_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_CPU_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing prg.");
end
--program flashfile to the cart
if program then
--open file
file = assert(io.open(flashfile, "rb"))
--determine if auto-doubling, deinterleaving, etc,
--needs done to make board compatible with rom
--flash cart
flash.write_file( file, 512, "MAP30", "PRGROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
file = assert(io.open(verifyfile, "wb"))
--dump cart into file
dump.dumptofile( file, 512, "MAP30", "PRGROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
mapper30.process = process
-- return the module's table
return mapper30

281
host/scripts/nes/mmc1.lua Normal file
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@ -0,0 +1,281 @@
-- create the module's table
local mmc1 = {}
-- import required modules
local dict = require "scripts.app.dict"
local nes = require "scripts.app.nes"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
-- file constants
-- local functions
local function init_mapper( debug )
--MMC1 ignores all but the first write
dict.nes("NES_CPU_RD", 0x8000)
--reset MMC1 shift register with D7 set
dict.nes("NES_CPU_WR", 0x8000, 0x80)
-- mmc1_write(0x8000, 0x10); //32KB mode, prg bank @ $8000-FFFF, 4KB CHR mode
dict.nes("NES_MMC1_WR", 0x8000, 0x10)
-- //note the mapper will constantly reset to this when writing to PRG-ROM
-- //PRG-ROM A18-A14
-- mmc1_write(0xE000, 0x00); //16KB bank @ $8000
dict.nes("NES_MMC1_WR", 0xE000, 0x00)
-- //CHR-ROM A16-12 (A14-12 are required to be valid)
-- mmc1_write(0xA000, 0x02); //4KB bank @ PT0 $2AAA cmd and writes
dict.nes("NES_MMC1_WR", 0xA000, 0x02)
-- mmc1_write(0xC000, 0x05); //4KB bank @ PT1 $5555 cmd fixed
dict.nes("NES_MMC1_WR", 0xC000, 0x05)
end
--test the mapper's mirroring modes to verify working properly
--can be used to help identify board: returns true if pass, false if failed
local function mirror_test( debug )
--put MMC1 in known state (mirror bits cleared)
init_mapper()
--MM = 0: 1 screen A
dict.nes("NES_MMC1_WR", 0x8000, 0x00)
if (nes.detect_mapper_mirroring() ~= "1SCNA") then
print("MMC1 mirror test fail")
return false
end
--MM = 1: 1 screen B
dict.nes("NES_MMC1_WR", 0x8000, 0x01)
if (nes.detect_mapper_mirroring() ~= "1SCNB") then
print("MMC1 mirror test fail")
return false
end
--MM = 2: Vertical
dict.nes("NES_MMC1_WR", 0x8000, 0x02)
if (nes.detect_mapper_mirroring() ~= "VERT") then
print("MMC1 mirror test fail")
return false
end
--MM = 3: Horizontal
dict.nes("NES_MMC1_WR", 0x8000, 0x03)
if (nes.detect_mapper_mirroring() ~= "HORZ") then
print("MMC1 mirror test fail")
return false
end
--passed all tests
if(debug) then print("MMC1 mirror test passed") end
return true
end
local function wr_flash_byte(addr, value, debug)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xAA)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x2AAA, 0x55)
dict.nes("DISCRETE_EXP0_PRGROM_WR", 0x5555, 0xA0)
dict.nes("DISCRETE_EXP0_PRGROM_WR", addr, value)
local rv = dict.nes("NES_CPU_RD", addr)
local i = 0
while ( rv ~= value ) do
rv = dict.nes("NES_CPU_RD", addr)
i = i + 1
end
if debug then print(i, "naks, done writing byte.") end
end
--read PRG-ROM flash ID
local function prgrom_manf_id( debug )
init_mapper()
if debug then print("reading PRG-ROM manf ID") end
--A0-A14 are all directly addressable in CNROM mode
--and mapper writes don't affect PRG banking
dict.nes("NES_CPU_WR", 0xD555, 0xAA)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xD555, 0x90)
rv = dict.nes("NES_CPU_RD", 0x8000)
if debug then print("attempted read PRG-ROM manf ID:", string.format("%X", rv)) end
rv = dict.nes("NES_CPU_RD", 0x8001)
if debug then print("attempted read PRG-ROM prod ID:", string.format("%X", rv)) end
--exit software
dict.nes("NES_CPU_WR", 0x8000, 0xF0)
end
--read CHR-ROM flash ID
local function chrrom_manf_id( debug )
init_mapper()
if debug then print("reading CHR-ROM manf ID") end
--A0-A14 are all directly addressable in CNROM mode
--and mapper writes don't affect PRG banking
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_PPU_WR", 0x1555, 0x90)
rv = dict.nes("NES_PPU_RD", 0x0000)
if debug then print("attempted read CHR-ROM manf ID:", string.format("%X", rv)) end
rv = dict.nes("NES_PPU_RD", 0x0001)
if debug then print("attempted read CHR-ROM prod ID:", string.format("%X", rv)) end
--exit software
dict.nes("NES_PPU_WR", 0x8000, 0xF0)
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for NES
dict.io("IO_RESET")
dict.io("NES_INIT")
--test cart by reading manf/prod ID
if test then
--verify mirroring is behaving as expected
mirror_test(true)
nes.ppu_ram_sense(0x1000, true)
print("EXP0 pull-up test:", dict.io("EXP0_PULLUP_TEST"))
--attempt to read PRG-ROM flash ID
prgrom_manf_id(true)
--attempt to read CHR-ROM flash ID
chrrom_manf_id(true)
end
--dump the cart to dumpfile
if read then
init_mapper() --32KB PRG-ROM banks
file = assert(io.open(dumpfile, "wb"))
--dump cart into file
dump.dumptofile( file, 128, "MMC1", "PRGROM", true )
dump.dumptofile( file, 128, "MMC1", "CHRROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
init_mapper()
print("\nerasing MMC1");
print("erasing PRG-ROM");
dict.nes("NES_CPU_WR", 0xD555, 0xAA)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xD555, 0x80)
dict.nes("NES_CPU_WR", 0xD555, 0xAA)
dict.nes("NES_CPU_WR", 0xAAAA, 0x55)
dict.nes("NES_CPU_WR", 0xD555, 0x10)
rv = dict.nes("NES_CPU_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_CPU_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing prg.");
--TODO erase CHR-ROM only if present
init_mapper()
print("erasing CHR-ROM");
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_PPU_WR", 0x1555, 0x80)
dict.nes("NES_PPU_WR", 0x1555, 0xAA)
dict.nes("NES_PPU_WR", 0x0AAA, 0x55)
dict.nes("NES_PPU_WR", 0x1555, 0x10)
rv = dict.nes("NES_PPU_RD", 0x8000)
local i = 0
--TODO create some function to pass the read value
--that's smart enough to figure out if the board is actually erasing or not
while ( rv ~= 0xFF ) do
rv = dict.nes("NES_PPU_RD", 0x8000)
i = i + 1
end
print(i, "naks, done erasing chr.");
end
--program flashfile to the cart
if program then
--open file
file = assert(io.open(flashfile, "rb"))
--determine if auto-doubling, deinterleaving, etc,
--needs done to make board compatible with rom
--flash cart
flash.write_file( file, 128, "MMC1", "PRGROM", true )
--flash.write_file( file, 128, "MMC1", "CHRROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
file = assert(io.open(verifyfile, "wb"))
--dump cart into file
dump.dumptofile( file, 128, "MMC1", "PRGROM", true )
dump.dumptofile( file, 128, "MMC1", "CHRROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
mmc1.process = process
-- return the module's table
return mmc1

53
host/scripts/nes/unrom.lua
View File

@ -20,7 +20,7 @@ local function init_mapper( debug )
--becomes catch 22 situation. Will have to rely on mcu over powering PRG-ROM.. --becomes catch 22 situation. Will have to rely on mcu over powering PRG-ROM..
--ahh but a way out would be to disable the PRG-ROM with exp0 (/WE) going low --ahh but a way out would be to disable the PRG-ROM with exp0 (/WE) going low
--for now the write below seems to be working fine though.. --for now the write below seems to be working fine though..
dict.nes("NES_CPU_WR", 0x8000, 0x80) dict.nes("NES_CPU_WR", 0x8000, 0x00)
end end
local function wr_flash_byte(addr, value, debug) local function wr_flash_byte(addr, value, debug)
@ -39,23 +39,60 @@ local function wr_flash_byte(addr, value, debug)
i = i + 1 i = i + 1
end end
if debug then print(i, "naks, done writing byte.") end if debug then print(i, "naks, done writing byte.") end
--TODO report error if write failed
end end
--base is the actual NES CPU address, not the rom offset (ie $FFF0, not $7FF0) --base is the actual NES CPU address, not the rom offset (ie $FFF0, not $7FF0)
local function wr_bank_table(base, entries) local function wr_bank_table(base, entries, numtables)
--UxROM can have a single bank table in $C000-FFFF (assuming this is most likely) local cur_bank
--or a bank table in all other banks in $8000-BFFF
--need to have A14 clear when lower bank enabled --need to have A14 clear when lower bank enabled
init_mapper() init_mapper()
--UxROM can have a single bank table in $C000-FFFF (assuming this is most likely)
--or a bank table in all other banks in $8000-BFFF
local i = 0 local i = 0
while( i < entries) do while( i < entries) do
wr_flash_byte(base+i, i) wr_flash_byte(base+i, i)
i = i+1; i = i+1;
end end
--[[
if( base >= 0xC000 ) then
--only need one bank table in last bank
cur_bank = entries - 1 --16 minus 1 is 15 = 0x0F
else
--need bank table in all banks except last
cur_bank = entries - 2 --16 minus 2 is 14 = 0x0E
end
while( cur_bank >= 0 ) do
--select bank to write to (last bank first)
--use the bank table to make the switch
dict.nes("NES_CPU_WR", base+cur_bank, cur_bank)
--write bank table to selected bank
local i = 0
while( i < entries) do
print("write entry", i, "bank:", cur_bank)
wr_flash_byte(base+i, i)
i = i+1;
end
cur_bank = cur_bank-1
if( base >= 0xC000 ) then
--only need one bank table in last bank
break
end
end
--]]
--TODO verify the bank table was successfully written before continuing! --TODO verify the bank table was successfully written before continuing!
end end
@ -135,9 +172,13 @@ local function process( test, read, erase, program, verify, dumpfile, flashfile,
--find bank table in the rom --find bank table in the rom
--write bank table to all banks of cartridge --write bank table to all banks of cartridge
--Nomolos' bank table is at $CC84 so hard code that for now --Nomolos' bank table is at $CC84 so hard code that for now
wr_bank_table(0xCC84, 32) --wr_bank_table(0xCC84, 32)
--Owlia bank table --Owlia bank table
--wr_bank_table(0xE473, 32) wr_bank_table(0xE473, 32)
--rushnattack
--wr_bank_table(0x8000, 8)
--twindragons
--wr_bank_table(0xC000, 32)
--flash cart --flash cart
flash.write_file( file, 512, "UxROM", "PRGROM", true ) flash.write_file( file, 512, "UxROM", "PRGROM", true )

261
host/scripts/snes/v3.lua Normal file
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@ -0,0 +1,261 @@
-- create the module's table
local v3 = {}
-- import required modules
local dict = require "scripts.app.dict"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
local snes = require "scripts.app.snes"
-- file constants
-- local functions
local function prgm_mode(debug)
if debug then print("going to program mode, swim:", snes_swimcart) end
if snes_swimcart then
print("ERROR cart got set to swim mode somehow!!!")
-- swim.snes_v3_prgm(debug)
else
dict.pinport("CTL_SET_LO", "SNES_RST")
end
end
local function play_mode(debug)
if debug then print("going to play mode, swim:", snes_swimcart) end
if snes_swimcart then
-- swim.snes_v3_play(debug)
print("ERROR cart got set to swim mode somehow!!!")
else
dict.pinport("CTL_SET_HI", "SNES_RST")
end
end
--local function wr_flash_byte(addr, value, debug)
--base is the actual NES CPU address, not the rom offset (ie $FFF0, not $7FF0)
--local function wr_bank_table(base, entries)
--Action53 not susceptible to bus conflicts, no banktable needed
-- Desc: attempt to read flash rom ID
-- Pre: snes_init() been called to setup i/o
-- Post:Address left on bus memories disabled
-- Rtn: true if flash ID found
local function read_flashID( debug )
local rv
--enter software mode A11 is highest address bit that needs to be valid
--datasheet not exactly explicit, A11 might not need to be valid
--part has A-1 (negative 1) since it's in byte mode, meaning the part's A11 is actually A12
--WR $AAA:AA $555:55 $AAA:AA
dict.snes("SNES_SET_BANK", 0x00)
--put cart in program mode
--v3.0 boards don't use EXP0 for program mode, must use SWIM via CIC
-- prgm_mode()
dict.snes("SNES_ROM_WR", 0x8AAA, 0xAA)
dict.snes("SNES_ROM_WR", 0x8555, 0x55)
dict.snes("SNES_ROM_WR", 0x8AAA, 0x90)
--exit program mode
-- play_mode()
--read manf ID
local manf_id = dict.snes("SNES_ROM_RD", 0x8000)
if debug then print("attempted read SNES ROM manf ID:", string.format("%X", manf_id)) end
--read prod ID
local prod_id = dict.snes("SNES_ROM_RD", 0x8002)
if debug then print("attempted read SNES ROM prod ID:", string.format("%X", prod_id)) end
local density_id = dict.snes("SNES_ROM_RD", 0x801C)
if debug then print("attempted read SNES density ID: ", string.format("%X", density_id)) end
local boot_sect = dict.snes("SNES_ROM_RD", 0x801E)
if debug then print("attempted read SNES boot sect ID:", string.format("%X", boot_sect)) end
--put cart in program mode
-- prgm_mode()
--exit software
dict.snes("SNES_ROM_WR", 0x0000, 0xF0)
--exit program mode
-- play_mode()
--return true if detected flash chip
if (manf_id == 0x01 and prod_id == 0x49) then
print("2MB flash detected")
return true
elseif (manf_id == 0x01 and prod_id == 0x7E) then
print("4-8MB flash detected")
return true
else
return false
end
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process( test, read, erase, program, verify, dumpfile, flashfile, verifyfile)
local rv = nil
local file
--initialize device i/o for SNES
dict.io("IO_RESET")
dict.io("SNES_INIT")
--test cart by reading manf/prod ID
if test then
--SNES detect HiROM or LoROM
--nes.detect_mapper_mirroring(true)
local snes_mapping = "LOROM"
--SNES detect if there's save ram and size
--SNES detect if able to read flash ID's
if not read_flashID(true) then
print("ERROR unable to read flash ID")
return
end
--quick lame check to see if chip erased
--[[
if snes.read_reset_vector(0, true) ~= 0xFFFF then
erase.erase_snes( false )
end
if snes.read_reset_vector( 1, true) ~= 0xFFFF then
erase.erase_snes( false )
end
if snes.read_reset_vector( 20, true) ~= 0xFFFF then
erase.erase_snes( false )
end
if snes.read_reset_vector( 63, true) ~= 0xFFFF then
erase.erase_snes( false )
end
--]]
end
--dump the cart to dumpfile
if read then
--initialize the mapper for dumping
init_mapper(debug)
file = assert(io.open(dumpfile, "wb"))
--TODO find bank table to avoid bus conflicts!
--dump cart into file
dump.dumptofile( file, 512, "LOROM", "SNESROM", true )
--close file
assert(file:close())
end
--erase the cart
if erase then
print("\nerasing tsop takes ~30sec");
local rv = nil
--WR $AAA:AA $555:55 $AAA:AA
dict.snes("SNES_SET_BANK", 0x00)
--put cart in program mode
-- snes.prgm_mode()
dict.snes("SNES_ROM_WR", 0x8AAA, 0xAA)
dict.snes("SNES_ROM_WR", 0x8555, 0x55)
dict.snes("SNES_ROM_WR", 0x8AAA, 0x80)
dict.snes("SNES_ROM_WR", 0x8AAA, 0xAA)
dict.snes("SNES_ROM_WR", 0x8555, 0x55)
dict.snes("SNES_ROM_WR", 0x8AAA, 0x10)
--exit program mode
-- snes.play_mode()
rv = dict.snes("SNES_ROM_RD", 0x8000)
local i = 0
while ( rv ~= 0xFF ) do
rv = dict.snes("SNES_ROM_RD", 0x8000)
i = i + 1
-- if debug then print(" ", i,":", string.format("%x",rv)) end
end
print(i, "naks, done erasing snes.");
--put cart in program mode
-- swim.start()
-- snes.prgm_mode()
--reset flash
dict.snes("SNES_ROM_WR", 0x8000, 0xF0)
--return to PLAY mode
-- print("erase play")
-- snes.play_mode()
-- print("erase play")
end
--program flashfile to the cart
if program then
--initialize the mapper for dumping
init_mapper(debug)
--open file
file = assert(io.open(flashfile, "rb"))
--determine if auto-doubling, deinterleaving, etc,
--needs done to make board compatible with rom
--not susceptible to bus conflicts
--flash cart
flash.write_file( file, 512, "LOROM", "SNESROM", true )
--close file
assert(file:close())
end
--verify flashfile is on the cart
if verify then
--for now let's just dump the file and verify manually
file = assert(io.open(verifyfile, "wb"))
--dump cart into file
dump.dumptofile( file, 512, "LOROM", "SNESROM", true )
--close file
assert(file:close())
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
v3.process = process
-- return the module's table
return v3

4
shared/shared_dict_buffer.h
View File

@ -139,8 +139,9 @@
#define MMC2 9 #define MMC2 9
#define MMC4 10 #define MMC4 10
#define CDREAM 11 #define CDREAM 11
#define CNINJA 12 //not actually mapper 12, just a temp mapper assignment
#define A53 28 #define A53 28
#define UNROM512 30 #define MAP30 30
#define EZNSF 31 #define EZNSF 31
#define BxROM 34 #define BxROM 34
#define RAMBO 64 #define RAMBO 64
@ -151,6 +152,7 @@
#define FME7 69 //SUNSOFT-5 with synth #define FME7 69 //SUNSOFT-5 with synth
#define HDIVER 78 #define HDIVER 78
#define DxROM 205 #define DxROM 205
#define DPROM 254 //just a random mapper number for whatever I need it for
// UNKNOWN 255 don't assign to something meaningful // UNKNOWN 255 don't assign to something meaningful
//operand LSB mapper variant //operand LSB mapper variant
#define NOVAR 0 #define NOVAR 0

5
shared/shared_dict_nes.h
View File

@ -39,6 +39,10 @@
//#define DISCRETE_EXP0_MAPPER_WR 0x03 //#define DISCRETE_EXP0_MAPPER_WR 0x03
#define NES_MMC1_WR 0x04
#define NES_DUALPORT_WR 0x05
//============================================================================================= //=============================================================================================
// OPCODES WITH OPERAND AND RETURN VALUE plus SUCCESS/ERROR_CODE // OPCODES WITH OPERAND AND RETURN VALUE plus SUCCESS/ERROR_CODE
//============================================================================================= //=============================================================================================
@ -62,5 +66,6 @@
#define MIR_VERT 0x12 #define MIR_VERT 0x12
#define MIR_HORZ 0x13 #define MIR_HORZ 0x13
#define NES_DUALPORT_RD 0x84 //RL=3
#endif #endif

8
shared/shared_dict_pinport.h
View File

@ -53,9 +53,9 @@
#define CTL_OD_ 24 #define CTL_OD_ 24
#define CTL_PP_ 25 #define CTL_PP_ 25
//operands //operands
// PC0 "MCO" mcu clock out M2/phi2, Sysclk, etc // PC0 "M2" NES M2/phi signal
#define C0_ 0 #define C0_ 0
#define MCO_ 0 #define M2_ 0
// PC1 "ROMSEL" Cartridge rom enable // PC1 "ROMSEL" Cartridge rom enable
#define C1_ 1 #define C1_ 1
#define ROMSEL_ 1 #define ROMSEL_ 1
@ -103,9 +103,9 @@
// PC15 "AUDR" cart audio // PC15 "AUDR" cart audio
#define C15_ 15 #define C15_ 15
#define AUDR_ 15 #define AUDR_ 15
// PC16 "CIN" CIC data in & GB power selector // PC16 "GBP" GB power selector
#define C16_ 16 #define C16_ 16
#define CIN_ 16 #define GBP_ 16
// PC17 "SWD" mcu debug // PC17 "SWD" mcu debug
#define C17_ 17 #define C17_ 17
#define SWD_ 17 #define SWD_ 17