diff --git a/shared/shared_pinport.h b/shared/shared_pinport.h index 4f6f16f..50984cb 100644 --- a/shared/shared_pinport.h +++ b/shared/shared_pinport.h @@ -9,6 +9,22 @@ //making this a shared file helps cut room for error as changing opcode numbers here will //inherently get forwarded to both firmware and app at same time. + + +//============================================================================================= +// OPCODES with no operand and no return value besides SUCCESS/ERROR_CODE +//============================================================================================= +// 0x00-0x7F +// 0-90: currently defined +// 19-22: unused due to accidentaly double defining CICE opcodes +// 91-127: not yet in use +// +// Current limit for these types of opcodes is 0-127 +// This allows for the MSB to be used for decoding pinport opcode to this type +// +//============================================================================================= +//============================================================================================= + //============================ //ADDR[7:0] PORTA //============================ @@ -181,12 +197,191 @@ //green had to separate these two with software. -/* default: - //macro doesn't exist on this PCB version - return ERROR_UNKWN_PINP_OPCODE; - } - - return SUCCESS; -}*/ + + +//============================================================================================= +// OPCODES WITH OPERAND and no return value besides SUCCESS/ERROR_CODE +//============================================================================================= +// 0x80-0x9F: opcodes with 8bit operand +// 0x80-83 are only ones currently in use +// 0xA0-0xAF: opcodes with 16bit operand +// 0xA0-A4 are only ones currently in use +// 0xB0-0xBF: opcodes with 24bit operand +// 0xA0 is currently only one in use +// +// +// Current limit for these types of opcodes is 128-191 (0x80-0xBF) +// This allows for the MSBs' to be used for decoding pinport opcode to this type +// +// +//============================================================================================= +//============================================================================================= + + +//================================= +//8bit operand +//================================= + +//ADDR[7:0] PORTA +#define ADDR_SET 0x80 + +//DATA[7:0] PORTB +#define DATA_SET 0x81 + +//ADDR[15:8] FLIPFLOP +//NES CPU: ADDRH[6:0] -> CPU A[14:8] +// ADDRH[7] -> NC on CPU side +//NES PPU: ADDRH[5:0] -> PPU A[13:8] +// ADDRH[6] -> NC on PPU side +// ADDRH[7] -> PPU /A13 (which drives CIRAM /CE on most carts "2-screen mirroring") +//SNES: ADDRH[7:0] -> CPU A[15:8] +#define ADDRH_SET 0x82 + +//EXPANSION FLIPFLOP +//NES: ADDRX[7:0] -> EXP PORT [8:1] +//SNES: ADDRX[7:0] -> CPU A[23:16] +#define ADDRX_SET 0x83 + +//Set ADDR/DATA bus DDR registers with bit granularity +// OP() IP() macros affect entire 8bit port's direction +// Each pin can be controlled individually though +// This could be useful for advanced feature that doesn't treat DATA/ADDR as byte wide port. +#define ADDR_DDR 0x84 +#define DATA_DDR 0x84 +//Perhaps it will be useful to have this function on other ports as well +//But probably wouldn't be very useful if standard carts are plugged in.. + +//TODO consider listing AVR internal registers here..? +//could be useful when utilizing SPI/I2C communications etc + + +//================================= +//16bit operand +//================================= + +//ADDR[15:0] (ADDRH:ADDR) +//Doesn't affect control signals +//bits[13:0] are applied to NES CPU, NES PPU, and SNES address bus +//bit[14] is only applied to CPU A14 on NES +//bit[15] is only applied to PPU /A13 on NES +//bit[15:14] are applied to SNES A[15:14] +#define ADDR16_SET 0xA0 + +//Set NES CPU ADDRESS BUS SET with /ROMSEL +//bit 15 is decoded to enable /ROMSEL properly (aka PRG /CE) +//bit15 is actually inverted then applied to /ROMSEL since /ROMSEL is low when NES CPU A15 is high +//NOTE! This does NOT affect M2 (aka phi2), so carts using M2 to decode things like WRAM is dependent on last value of M2 +//This will also stop current value of PPU /A13 with bit15 +#define NCPU_ADDR_ROMSEL 0xA1 + +//Set NES CPU ADDRESS BUS SET with M2 +//Identical to NCPU_ADDR_ROMSEL above, but M2 (aka phi2) affected instead of /ROMSEL +//bit 15 is decoded to assert M2 properly +//bit15 is actually applied directly to M2 since carts use M2 being high as part of A15=1 detection +//NOTE! This does NOT affect /ROMSEL, so /ROMSEL is whatever value it was previously +//This will also stop current value of PPU /A13 with bit15 +#define NCPU_ADDR_M2 0xA2 + +//Set NES CPU ADDRESS BUS SET with M2 & /ROMSEL +//Combination of opcodes above, but M2 and /ROMSEL will be asserted +//bit 15 is decoded to assert M2 & /ROMSEL properly +//bit15 is actually applied directly to M2 since carts use M2 being high as part of A15=1 detection +//NOTE! This does NOT affect /ROMSEL, so /ROMSEL is whatever value it was previously +//This will also stop current value of PPU /A13 with bit15 +#define NCPU_ADDR_M2ROMSEL 0xA3 + +//TODO consider opcode that preserves PPU /A13 instead of stomping it like the opcodes above. +//Can't think of why this would be useful so ignoring for now +//One reason might be to keep VRAM silent on a NES board with 4screen mirroring.. +// But should be able to do this with CHR /RD in same manner CHR-ROM is kept silent.. + +//Set NES PPU ADDRESS BUS with /A13 +//PPU address bus is 14bits wide A[13:0] so operand bits [15:14] are ignored. +//bit 13 is inverted and applied to PPU /A13 +//PPU control signals CHR /RD and CHR /WR are unaffected +//Note: since PPU /A13 is tied to ADDRH[7] could perform this faster by using ADDR16_SET +// but this opcode is convienent and ensures PPU /A13 is always inverse of PPU A13 +// This is important for NES carts with on board CHR-ROM and VRAM for 4screen mirroring. +#define NPPU_ADDR_SET 0xA4 + +//TODO consider opcode that sets PPU A[12:0] and maintains previous value of A13 & /A13 +//might be useful if trying to latch/clock CHR memory with it's /CE pin instead of /OE /WE + +//================================= +//24bit operand +//================================= + +//ADDR[23:0] (ADDRX:ADDRH:ADDR) SNES full address bus +//Sets SNES 24 bit address but to value of 24bit operand +//No control signals are modified +#define ADDR24_SET 0xB0 + + + + +//============================================================================================= +// OPCODES with NO OPERAND but have RETURN VALUE plus SUCCESS/ERROR_CODE +//============================================================================================= +// 0xC0-0xCF: opcodes with 8bit operand +// 0x80-83 are only ones currently in use +// 0xA0-0xAF: opcodes with 16bit operand +// 0xA0-A4 are only ones currently in use +// 0xB0-0xBF: opcodes with 24bit operand +// 0xA0 is currently only one in use +// +// +// Current limit for these types of opcodes is 192-255 (0xC0-0xFF) +// This allows for the MSBs' to be used for decoding pinport opcode to this type +// +// +//============================================================================================= +//============================================================================================= + + +//READ MCU I/O PORT INPUT 'PIN' REGISTERS +//This is what's used to read bus after setting DDR register to input with IP() command/macro +//Current value of PORT Determines if pullups are activated or not, pull up with HI() macro, and float with LO() macro +//ADDR[7:0] PINA +#define ADDR_PIN 0xC1 +//DATA[7:0] PINB +#define DATA_PIN 0xC0 +//CTL PINC +//Should set pin of interest to input with IP with macros prior to reading +//you're still allowed to read value even if some/all pins are output though +#define CTL_PIN 0xC2 +//AUX PIND +//Should set pin of interest to input with IP with macros prior to reading +//you're still allowed to read value even if some/all pins are output though +#define AUX_PIN 0xC3 + + +//READ MCU I/O PORT OUTPUT 'PORT' REGISTERS +//Gives means to see what pins are currently being driven (or pulled up) to. +//ADDR[7:0] PORTA +#define ADDR_PORT 0xC4 +//DATA[7:0] PORTB +#define DATA_PORT 0xC5 +//CTL PORTC +#define CTL_PORT 0xC6 +//AUX PORTD +#define AUX_PORT 0xC7 + + +//READ MCU I/O PORT DIRECTION 'DDR' REGISTERS +//Gives means to see what pins are currently set to I/P or O/P. +//ADDR[7:0] DDRA +#define ADDR_DDR 0xC8 +//DATA[7:0] DDRB +#define DATA_DDR 0xC9 +//CTL DDRC +#define CTL_DDR 0xCA +//AUX DDRD +#define AUX_DDR 0xCB + + + +//TODO consider listing AVR internal registers here..? +//could be useful when utilizing SPI/I2C communications etc + #endif