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INL-retro-progdump
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modified: Makefile 

-modified to caluclate ROM/RAM usage of atmega164a

new file:   source/io.h
new file:   source/logic.h
	-created files

modified:   source/io.c
modified:   source/main.c
	-created io_pullup going to make separate io inits based on cartridge inserted
	-modifing for io.h

modified:   source/pinport.h
	-File mostly complete with all possible pin manipulations
This commit is contained in:
paul eeepc 2016-11-22 20:27:52 -06:00
parent f973d990cd
commit b43b3c0756
6 changed files with 176 additions and 116 deletions
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3
firmware/Makefile
View File

@ -61,7 +61,8 @@ main.elf: shared $(OBJECTS)
main.hex: main.elf
rm -f main.hex main.eep.hex
avr-objcopy -j .text -j .data -O ihex main.elf main.hex
avr-size main.hex
avr-size -C --mcu=${DEVICE} main.elf
# avr-size main.hex
# debugging targets:

43
firmware/source/io.c
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@ -1,30 +1,35 @@
#include "io.h"
#include <avr/io.h>
#include "pinport.h"
//Goal is to silience everything
//Clear busses and pull up when able
void io_init()
//pullup as many cart pins as possible
//goal to be safe state for all hardware
void io_pullup()
{
//pull up data bus
DATA_IP();
DATA_HI();
//pull up addr[7:0] bus
ADDR_IP();
ADDR_HI();
//EXP0 input no pullup
//SNES /RESET pin disables SRAM on first few pcb versions
//NES PRG-ROM /OE on old INL-ROM v1 boards w/pulldown
//NED PRG-ROM /WE on INL-ROM v3 boards w/pullup
//NES CPLD JTAG TDO non-5v tolerant
EXP0_IP();
EXP0_LO();
//pull up data bus
DATA_IP();
DATA_HI();
//IRQ pullup NES boards will drive this pin
IRQ_IP();
IRQ_HI();
//pull up control port
CTL_IP();
CTL_HI();
//pull up aux port
AUX_IP();
AUX_HI();
//Aux port EXP /OE control
//pull up on EXP FF should disable FF ouput
//EXP0 input no pullup
//Lots of possibilities, ~safe bet it will have it's own pull-up/down if needed.
//SNES /RESET pin disables SRAM on first few pcb versions
//NES PRG-ROM /OE (with pulldown) on old INL-ROM v1 boards w/pulldown
//NED PRG-ROM /WE (with pullup) on INL-ROM v3 boards w/pullup
//NES CPLD JTAG TDO non-5v tolerant
EXP0_FLT();
//LED LAST displaying complete..
}

9
firmware/source/io.h Normal file
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@ -0,0 +1,9 @@
#ifndef _io_h
#define _io_h
#include <avr/io.h>
#include "pinport.h"
void io_pullup();
#endif

6
firmware/source/logic.h Normal file
View File

@ -0,0 +1,6 @@
#define LO 0x00
#define HI 0xFF
#define TRUE 0x00
//FALSE is ANYTHING but TRUE, the value signifies the error number

15
firmware/source/main.c
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@ -4,8 +4,8 @@
#include <util/delay.h>
#include "usbdrv.h"
#include "macro.h"
#include "usb_commands.h"
#include "io.h"
#include "shared_usb_commands.h"
//USB_PUBLIC usbMsgLen_t usbFunctionSetup(uchar data[8]);
@ -124,13 +124,13 @@ int main()
usbDeviceConnect();
//intialize i/o to default state
io_init();
//intialize i/o to pullup state
io_pullup();
//configure LED PORT/DDR
//SETUP_LED();
//Always startup with LED ON
//LED_ON();
LED_OP();
//boot with LED on to differentiate bettwen BL/RUN
LED_ON();
//enable interrupts
sei();
@ -150,4 +150,3 @@ int main()
return 0;
}

216
firmware/source/pinport.h
View File

@ -1,12 +1,21 @@
#include <avr/io.h>
#include "logic.h"
//This file contains pinout translations from AVR names to "kazzo" names
//this file also works to make all kazzo versions compatible and "alike"
//There are defines for kazzo version, turns out unique early versions
//can be differentiated by solder mask color.
//Final version is default and doesn't need any defines
//#define PURPLE_KAZZO
//#define GREEN_KAZZO
//=======================================================
//History of PCB revsisions produced by InfiniteNesLives
//=======================================================
//
// uncomment define if buiding for either of the first two versions
//#define PURPLE_KAZZO
// First printed circuit board version
// only handful made (less than 10?)
// Purple solder mask
@ -31,6 +40,9 @@
// and jumper closed..
// Believe I closed this jumper on units I shipped
// prob should have left it open..
// Suggested fix: leave open and ground EXP9
// -prevents issue with LED when FC cart inserted
// -minor draw back no access to EXP9
// ALOG - EXP6 - DIGI jumper
// another noob jumper decision...
// ALOG is the MCU AREF pin which should be tied to VCC
@ -64,6 +76,9 @@
// -Same as version above as far as I know.
//
//
// uncomment define if buiding for this versions
//#define GREEN_KAZZO
//
// Third printed circuit board version
// only handful made (about ten?) used primarily as SNES prototype
// Green solder mask
@ -84,8 +99,8 @@
// instead it's controlled by A20 (EXPFF Q4)
// prevents putting INL SNES boards in program mode unless A20 is also low
// pretty much makes flashing SNES boards a royal PITA/impossible
// would have to free /RESET and wire to EXP0/PD0 to flash INL SNES board.
//
// Suggested fix is to have PD0 (EXP0) control SNES /RESET
// would have to free /RESET and wire to EXP0/PD0 to permit flashing/reading INL SNES board.
//
//
// Fourth printed circuit board version
@ -127,6 +142,7 @@
// Orange solder mask
// Labeled "Retro programmer/dumper v1.4" "Kazzo 1.x"
// Dated OCT 2016
// Addition of fancy INL logo for first time
// * Includes NES, Famicom, & SNES connector
// * SNES connector improvement to correct pitch issue with prev ver.
// * Addition of PCT resettable fuse on incoming power.
@ -137,10 +153,6 @@
// -None from previous version
//
#define LO 0x00
#define HI 0xFF
//#define TRUE 0x00
//FALSE is ANYTHING but TRUE, the value signifies the error number
//============================
@ -153,8 +165,8 @@
//DDR-PORT MACROS
#define ADDR_IP() ADDR_DDR = LO
#define ADDR_OP() ADDR_DDR = HI
#define ADDR_HI() ADDR_OUT = HI
#define ADDR_LO() ADDR_OUT = LO
#define ADDR_HI() ADDR_OUT = HI
//============================
@ -167,8 +179,8 @@
//DDR-PORT MACROS
#define DATA_IP() DATA_DDR = LO
#define DATA_OP() DATA_DDR = HI
#define DATA_HI() DATA_OUT = HI
#define DATA_LO() DATA_OUT = LO
#define DATA_HI() DATA_OUT = HI
//============================
@ -181,61 +193,94 @@
//DDR-PORT MACROS
#define CTL_IP() CTL_DDR = LO
// No CTL_OP() macro as some of these are inputs or bidir, best to individually assert as output
#define CTL_HI() CTL_OUT = HI
#define CTL_LO() CTL_OUT = LO
//OLD CODE //AHL, AXL, are always output and high, unless individually asserted.
// #define CTL_IP() CTL_DDR = 0b10001000// &= ((1<<AHL) | (1<<AXL))
// #define CTL_OP() CTL_DDR = 0b10111111 //&= ~(1<<CICE); CTL_DDR |= ~((1<<AHL) | (1<<AXL) | (1<<CICE)) //CIRAM /CE is always input
// #define CTL_HI() CTL_OUT |= ~((1<<AHL) | (1<<AXL))
// //maintain these high unless individually asserted
// #define CTL_LO() CTL_OUT &= ((1<<AHL) | (1<<AXL))
#define CTL_HI() CTL_OUT = HI
//PIN DEFN
#define M2 PC0 //NES, FC, & SNES (SYSCLK)
#define ROMSEL PC1 //(aka PRG/CE) NES, FC, & SNES
#define PRGRW PC2 //PRG R/W on NES & FC
#ifdef PURPLE_KAZZO
#define p_AXL PC3 //EXP FF CLK on purple boards
#else
#define FREE PC3 //Free pin on all other boards
#endif
#define C_RD PC4 //NES & FC CHR /RD
#define S_RD PC4 //SNES /RD
#define C_WR PC5 //NES & FC CHR /WR
#define S_WR PC5 //SNES /WR
#define CICE PC6 //NES & FC CIRAM /CE, most carts are 2screen tying this to CHR A13 making this an I/P
#define CSRD PC4 //NES & FC CHR /RD, SNES /RD
#define CSWR PC5 //NES & FC CHR /WR, SNES /WR
#define CICE PC6 //NES & FC CIRAM /CE, most carts are 2screen tying this to CHR /A13 making this an I/P
#ifdef GREEN_KAZZO
#define g_AXHL PC7 //Both ADDR_MID & EXP/ADDRHI FF CLK on green prototype
#else
#define AHL PC7 //ADDR MID FF CLK per orig kazzo design
#define g_AXL PC7 //Also EXP/ADDRHI FF CLK on green prototype
#endif
//PIN MACROS
#define M2_IP() CTL_DDR &= ~(1<<M2)
#define M2_OP() CTL_DDR |= (1<<M2)
#define M2_HI() CTL_OUT |= (1<<M2)
#define M2_LO() CTL_OUT &= ~(1<<M2)
#define M2_HI() CTL_OUT |= (1<<M2)
//TODO read M2 PIN as input
#define ROMSEL_IP() CTL_DDR &= ~(1<<ROMSEL)
#define ROMSEL_OP() CTL_DDR |= (1<<ROMSEL)
#define ROMSEL_HI() CTL_OUT |= (1<<ROMSEL)
#define ROMSEL_LO() CTL_OUT &= ~(1<<ROMSEL)
#define ROMSEL_HI() CTL_OUT |= (1<<ROMSEL)
#define CICE_IP() CTL_DDR &= ~(1<<CICE)
#define CICE_OP() CTL_DDR |= (1<<CICE)
#define CICE_HI() CTL_OUT |= (1<<CICE)
#define CICE_LO() CTL_OUT &= ~(1<<CICE)
//#define PU_CICE() CTL_DDR &= ~(1<<CICE); CTL_OUT |= (1<<CICE);
#define CICE_HI() CTL_OUT |= (1<<CICE)
#define PRGRW_IP() CTL_OUT &= ~(1<<PRGRW)
#define PRGRW_OP() CTL_OUT |= (1<<PRGRW)
#define PRGRW_RD() CTL_OUT |= (1<<PRGRW) //HI for reads
#define PRGRW_IP() CTL_DDR &= ~(1<<PRGRW)
#define PRGRW_OP() CTL_DDR |= (1<<PRGRW)
#define PRGRW_WR() CTL_OUT &= ~(1<<PRGRW) //LO for writes
#define PRGRW_RD() CTL_OUT |= (1<<PRGRW) //HI for reads
// //SNES copy cart needs CIRAM A10 and CIRAM /CE to be outputs
// #define CC_OP() AUX_DDR |= (1<<CIA10); CTL_DDR |= (1<<CICE)
// #define CC_IP() AUX_DDR &= ~(1<<CIA10); CTL_DDR &= ~(1<<CICE)
#ifdef p_AXL
#define p_AXL_IP() CTL_DDR &= ~(1<<p_AXL)
#define p_AXL_OP() CTL_DDR |= (1<<p_AXL)
#define p_AXL_lo() CTL_OUT &= ~(1<<p_AXL) //Don't recommend calling lo/hi, use CLK instead
#define p_AXL_hi() CTL_OUT |= (1<<p_AXL)
//AXL_CLK assumes AXL was previously left in default low state
#define AXL_CLK() p_AXL_hi(); p_AXL_lo(); //same name and convention on final design
#else //Green and final design
#define FREE_IP() CTL_DDR &= ~(1<<FREE)
#define FREE_OP() CTL_DDR |= (1<<FREE)
#define FREE_LO() CTL_OUT &= ~(1<<FREE)
#define FREE_HI() CTL_OUT |= (1<<FREE)
#endif
#define CSRD_IP() CTL_DDR &= ~(1<<CSRD)
#define CSRD_OP() CTL_DDR |= (1<<CSRD)
#define CSRD_LO() CTL_OUT &= ~(1<<CSRD)
#define CSRD_HI() CTL_OUT |= (1<<CSRD)
#define CSWR_IP() CTL_DDR &= ~(1<<CSWR)
#define CSWR_OP() CTL_DDR |= (1<<CSWR)
#define CSWR_LO() CTL_OUT &= ~(1<<CSWR)
#define CSWR_HI() CTL_OUT |= (1<<CSWR)
#define CICE_IP() CTL_DDR &= ~(1<<CICE)
#define CICE_OP() CTL_DDR |= (1<<CICE)
#define CICE_LO() CTL_OUT &= ~(1<<CICE)
#define CICE_HI() CTL_OUT |= (1<<CICE)
#ifdef g_AXHL
#define g_AXHL_IP() CTL_DDR &= ~(1<<g_AXHL)
#define g_AXHL_OP() CTL_DDR |= (1<<g_AXHL)
#define g_AXHL_lo() CTL_OUT &= ~(1<<g_AXHL) //Don't recommend calling these as AXHL should be left low
#define g_AXHL_hi() CTL_OUT |= (1<<g_AXHL) //That way AXHL_CLK(); is always effective
#define AXHL_CLK() g_AXHL_hi(); g_AXHL_lo();
#else //purple and final design
#define AHL_IP() CTL_DDR &= ~(1<<AHL)
#define AHL_OP() CTL_DDR |= (1<<AHL)
#define AHL_lo() CTL_OUT &= ~(1<<AHL) //Don't recommend calling these as AHL should be left low
#define AHL_hi() CTL_OUT |= (1<<AHL) //That way AHL_CLK(); is always effective
#define AHL_CLK() AHL_hi(); AHL_lo();
#endif
//============================
//AUX PORTD
@ -247,11 +292,11 @@
//DDR-PORT MACROS
#define AUX_IP() AUX_DDR &= ((1<<USBP) | (1<<USBM)) //Don't touch USB pins!!!
// No AUX_OP() macro as many of these are inputs or bidir, best to individually assert as output
#define AUX_HI() AUX_OUT |= ~((1<<USBP) | (1<<USBM))
#define AUX_LO() AUX_OUT &= ((1<<USBP) | (1<<USBM))
#define AUX_HI() AUX_OUT |= ~((1<<USBP) | (1<<USBM))
//PIN DEFN
#define EXP0 PD0 //NES EXP0
#define EXP0 PD0 //NES EXP0 controls a number of varying flash cart features...
#define FC_APU PD0 //FC Audio in cart from 2A03 APU
#define TDO PD0 //CPLD JTAG on INL-ROM NES/FC boards released after ~Oct2016
#define S_RST PD0 //SNES /RESET pin used for CPLD prgm/play mode and SRAM CE
@ -265,65 +310,60 @@
#define CIA10 PD5 //NES & FC CIRAM A10 (aka VRAM A10)
#define BL PD6 //Bootloader switch BL->GND, RUN->float
#define p_XOE PD7 //EXP/ADDRHI FF /OE pin on purple and green boards
#ifdef PURPLE_KAZZO
#define pg_XOE PD7 //EXP/ADDRHI FF /OE pin on purple and green boards
#endif
#ifdef GREEN_KAZZO
#define pg_XOE PD7 //EXP/ADDRHI FF /OE pin on purple and green boards
#endif
#ifndef pg_XOE //FINAL_DESIGN
#define AXLOE PD7 //EXP/ADDRHI FF CLK & /OE pin on final board versions
#endif
//PIN MACROS
// //EXP0 to only be pulled high because XO boards don't level shift EXP0
// //EXP0_LO(); replace with EXP0_LO(); EXP0_OP();
// //EXP0_HI(); replace with EXP0_IP(); EXP0_HI();
// #define EXP0_IP() AUX_DDR &= ~(1<<EXP0)
// #define EXP0_OP() AUX_DDR |= (1<<EXP0)
// #define EXP0_HIGH() AUX_OUT |= (1<<EXP0)
// #define EXP0_LOW() AUX_OUT &= ~(1<<EXP0)
// #define EXP0_HI() EXP0_IP(); EXP0_HIGH(); NOP(); NOP(); NOP(); NOP();
// #define EXP0_LO() EXP0_LOW(); EXP0_OP();
//lower case aren't meant to be called unless certain pin is 5v tolerant
#define EXP0_ip() AUX_DDR &= ~(1<<EXP0)
#define EXP0_op() AUX_DDR |= (1<<EXP0)
#define EXP0_lo() AUX_OUT &= ~(1<<EXP0) //Don't call this assuming EXP0 DDR is set to o/p
#define EXP0_hi() AUX_OUT |= (1<<EXP0) //Don't call this unless you're certain pin is 5v tolerant
//User options pull up, force low, and float
#define EXP0_LO() EXP0_lo(); EXP0_op(); //Sets low then DDR to o/p
#define EXP0_PU() EXP0_ip(); EXP0_hi(); //maybe add some NOP() to allow time for pull up
#define EXP0_FLT() EXP0_ip(); EXP0_lo(); //Set to i/p w/o pullup
#define ENABLE_LED() AUX_DDR |= (1<<LED)
#define DISABLE_LED() AUX_DDR &= ~(1<<LED)
#define LED_ON() AUX_OUT |= (1<<LED)
#define LED_IP() AUX_DDR &= ~(1<<LED)
#define LED_OP() AUX_DDR |= (1<<LED)
#define LED_OFF() AUX_OUT &= ~(1<<LED)
#define LED_ON() AUX_OUT |= (1<<LED)
//#define SETUP_ADDR_X() AUX_DDR |= (1<<XOE)
//#define DISABLE_ADDR_X() AUX_OUT |= (1<<XOE)
//#define ENABLE_ADDR_X() AUX_OUT &= ~(1<<XOE)
//
//#define SETUP_AHL() CTL_DDR |= (1<<AHL); CTL_OUT |= (1<<AHL) //output high
//#define SETUP_AXL() CTL_DDR |= (1<<AXL); CTL_OUT |= (1<<AXL) //output high
//#define LATCH_AHL() CTL_OUT &= ~(1<<AHL); CTL_OUT |= (1<<AHL) //toggle low -> high
//#define LATCH_AXL() CTL_OUT &= ~(1<<AXL); CTL_OUT |= (1<<AXL) //toggle low -> high
// #define PRG_RD_PCE_HI() CTL_OUT |= (1<<PRW) | (1<<PCE)
// #define PRG_WR_PCE_LO() CTL_OUT &= ~((1<<PRW) | (1<<PCE))
//
// //#define SNES_RD_SEL_HI() CTL_OUT |= (1<<CRD) | (1<<PCE)
// #define SNES_WR_SEL_LO() CTL_OUT &= ~((1<<CWR) | (1<<PCE))
// #define SNES_RD_SEL_LO() CTL_OUT &= ~((1<<CRD) | (1<<PCE))
// #define SNES_CTL_HI() CTL_OUT |= (1<<CWR) | (1<<CRD) | (1<<PCE)
// #define CC_CTL_HI() CTL_OUT |= (1<<PRW) | (1<<CICE); AUX_OUT |= (1<<CIA10)
// //#define SNES_CTL_LO() CTL_OUT &= ~((1<<CWR) | (1<<CRD) | (1<<PCE))
//
// #define CHR_OEN() CTL_OUT |= (1<<CRD)
// #define CHR_OE() CTL_OUT &= ~(1<<CRD)
// #define CHR_WEN() CTL_OUT |= (1<<CWR) //Not-able (high)
// #define CHR_WE() CTL_OUT &= ~(1<<CWR) //Enabled (low)
//
// #define CC_OEN() AUX_OUT |= (1<<CIA10)
// #define CC_OE() AUX_OUT &= ~(1<<CIA10)
// #define CC_WEN() CTL_OUT |= (1<<PRW) //Not-able (high)
// #define CC_WE() CTL_OUT &= ~(1<<PRW) //Enabled (low)
//
// #define CHR_RD() CHR_WEN(); CHR_OE();
// #define CHR_WR() CHR_OEN(); CHR_WE(); // /OE-hi /WE-lo
//
// // /WE-hi /OE-lo
// // PRG RW hi, CIRAMA10 lo
// #define CC_RD() CC_WEN(); CC_OE();
// #define CC_WR() CC_OEN(); CC_WE();
// //CIRAM A10 hi, PRGRW lo
// // /OE-hi /WE-lo
#define IRQ_IP() AUX_DDR &= ~(1<<IRQ)
#define IRQ_OP() AUX_DDR |= (1<<IRQ)
#define IRQ_LO() AUX_OUT &= ~(1<<IRQ)
#define IRQ_HI() AUX_OUT |= (1<<IRQ)
#define CIA10_IP() AUX_DDR &= ~(1<<CIA10)
#define CIA10_OP() AUX_DDR |= (1<<CIA10)
#define CIA10_LO() AUX_OUT &= ~(1<<CIA10)
#define CIA10_HI() AUX_OUT |= (1<<CIA10)
#define BL_IP() AUX_DDR &= ~(1<<BL)
#define BL_OP() AUX_DDR |= (1<<BL)
#define BL_LO() AUX_OUT &= ~(1<<BL)
#define BL_HI() AUX_OUT |= (1<<BL)
#ifndef pg_XOE //FINAL_DESIGN
#define AXLOE_IP() AUX_DDR &= ~(1<<AXLOE)
#define AXLOE_OP() AUX_DDR |= (1<<AXLOE)
#define EXPFF_OP() AUX_OUT &= ~(1<<AXLOE) //FF /OE pin low->enable o/p
#define EXPFF_FLT() AUX_OUT |= (1<<AXLOE) //FF /OE pin high->disable o/p
//Caution AXL_CLK() relies on EXPFF_OP() to be called beforehand
// Think of it like you must enable the output before you can clock it.
// Floating EXPFF also happens to clock it. Think of it like it looses it's value if disabled.
#define AXL_CLK() EXPFF_FLT(); EXPFF_OP(); //same name and convention as purple
#else //purple and green versions
#define XOE_IP() AUX_DDR &= ~(1<<pg_XOE)
#define XOE_OP() AUX_DDR |= (1<<pg_XOE)
#define EXPFF_OP() AUX_OUT &= ~(1<<pg_XOE) //FF /OE pin low->enable o/p
#define EXPFF_FLT() AUX_OUT |= (1<<pg_XOE) //FF /OE pin high->disable o/p
#endif