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Big ol' commit with addition of support for GBA, Genesis, & N64 

cartridge reading!

have some cleanup to do:
clean up sega dumping so don't need a page0/1
implement sega single reads

Add GBA to some of the common opcodes

dumping Don't think need addrH |= of mapper, but maybe this is key to
cleaning up first note..

gba, sega, n64 has extra NOPs, remove and test.

create pinport renames for sega pins, move mask defines to pinport.h

clean up comments for genesis page reads..
This commit is contained in:
Paul XPS 2018-12-08 16:01:59 -06:00
parent fa71e2ef2a
commit c1b35baf06
25 changed files with 2488 additions and 1548 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

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@ -1,7 +1,7 @@
Archive member included to satisfy reference by file (symbol)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
C:\Users\paul\AppData\Local\Temp\ccekVufX.o (__aeabi_unwind_cpp_pr0)
C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o (__aeabi_unwind_cpp_pr0)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(libunwind.o)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o) (restore_core_regs)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
@ -51,9 +51,9 @@ c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o) (_exit)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o (__gnu_thumb1_case_uqi)
C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o (__gnu_thumb1_case_uqi)
c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o)
C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o (__gnu_thumb1_case_uhi)
C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o (__gnu_thumb1_case_uhi)
Allocating common symbols
Common symbol size file
@ -107,6 +107,7 @@ pbje_numclk 0x1 source/jtag.o (symbol from plugin)
__lock___dd_hash_mutex
0x1 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-lock.o)
__lock___tz_mutex 0x1 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-lock.o)
n64_bank 0x2 source/n64.o (symbol from plugin)
pbje_data 0x20 source/jtag.o (symbol from plugin)
__lock___sfp_recursive_mutex
0x1 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-lock.o)
@ -131,39 +132,39 @@ Discarded input sections
.ARM.exidx 0x00000000 0x8 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
.ARM.attributes
0x00000000 0x1b c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
.text 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.bss 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.stack 0x00000000 0xc00 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.heap 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.debug_line 0x00000000 0x7c C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.debug_info 0x00000000 0x22 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.debug_abbrev 0x00000000 0x12 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.text 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.bss 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.stack 0x00000000 0xc00 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.heap 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.debug_line 0x00000000 0x7c C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.debug_info 0x00000000 0x22 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.debug_abbrev 0x00000000 0x12 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.debug_aranges
0x00000000 0x28 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.debug_str 0x00000000 0x68 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
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0x00000000 0x28 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.debug_str 0x00000000 0x68 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.debug_ranges 0x00000000 0x20 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.ARM.attributes
0x00000000 0x1b C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.text 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
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.ARM.extab 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccekVufX.o
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.debug_abbrev 0x00000000 0x14 C:\Users\paul\AppData\Local\Temp\ccekVufX.o
0x00000000 0x1b C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.text 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text 0x00000000 0x4 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
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.ARM.extab 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.ARM.exidx 0x00000000 0x8 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.debug_line 0x00000000 0x49 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.debug_info 0x00000000 0x26 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.debug_abbrev 0x00000000 0x14 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.debug_aranges
0x00000000 0x20 C:\Users\paul\AppData\Local\Temp\ccekVufX.o
.debug_str 0x00000000 0x65 C:\Users\paul\AppData\Local\Temp\ccekVufX.o
0x00000000 0x20 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.debug_str 0x00000000 0x65 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.ARM.attributes
0x00000000 0x21 C:\Users\paul\AppData\Local\Temp\ccekVufX.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.bss 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.ARM.extab 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
0x00000000 0x21 C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
.data 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.bss 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.ARM.extab 0x00000000 0x0 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.data 0x00000000 0x0 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.bss 0x00000000 0x0 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.debug_frame 0x00000000 0x2b4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
@ -426,10 +427,10 @@ Linker script and memory map
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtbegin.o
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m/crt0.o
LOAD C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
LOAD C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
LOAD C:\Users\paul\AppData\Local\Temp\ccekVufX.o
LOAD C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
LOAD C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
LOAD C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
LOAD C:\Users\paul\AppData\Local\Temp\ccA8zOw8.o
LOAD C:\Users\paul\AppData\Local\Temp\ccobfpka.o
START GROUP
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a
@ -443,17 +444,17 @@ END GROUP
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtend.o
LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crtn.o
.text 0x08000000 0x5210
.text 0x08000000 0x5570
*(.isr_vector)
.isr_vector 0x08000000 0xc0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.isr_vector 0x08000000 0xc0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
0x08000000 __isr_vector
*(.usb_driver)
.usb_driver 0x080000c0 0x3bc C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.usb_driver 0x080000c0 0x3bc C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x08000198 USB_IRQHandler
*(.usb_desc)
.usb_desc 0x0800047c 0xb8 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.usb_desc 0x0800047c 0xb8 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*(.hardfault)
.hardfault 0x08000534 0x2 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.hardfault 0x08000534 0x2 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
0x08000534 TIM1_CC_IRQHandler
0x08000534 TSC_IRQHandler
0x08000534 ADC1_COMP_IRQHandler
@ -492,7 +493,7 @@ LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eab
0x08000534 USART1_IRQHandler
0x08000534 TIM1_BRK_UP_TRG_COM_IRQHandler
*fill* 0x08000536 0x2 ff
.hardfault 0x08000538 0xc C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.hardfault 0x08000538 0xc C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x08000538 HardFault_Handler
*_thumb1_case_uqi.o()
.text 0x08000544 0x14 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uqi.o)
@ -508,11 +509,11 @@ LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eab
0x0800058c 0x1e c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(_thumb1_case_uhi.o)
*(.fw_update)
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.fw_update 0x080005ac 0x150 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.fw_update 0x080005ac 0x150 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x00000770 . = 0x770
*fill* 0x080006fc 0x74 ff
*(.fw_up_main)
.fw_up_main 0x08000770 0x70 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.fw_up_main 0x08000770 0x70 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x00000800 . = 0x800
*fill* 0x080007e0 0x20 ff
*(.appver)
@ -520,174 +521,177 @@ LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eab
*fill* 0x08000800 0x4 ff
*(.reset_handler)
.reset_handler
0x08000804 0x3c C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
0x08000804 0x3c C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
0x08000804 Reset_Handler
*(.usbFuncWrite)
.usbFuncWrite 0x08000840 0x44 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.usbFuncWrite 0x08000840 0x44 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*(.usbFuncSetup)
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*(.text*)
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.text.cnrom_chrrom_flash_wr
0x08002a64 0x7c C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002d0c 0x7c C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.nes_cpu_rd
0x08002ae0 0x40 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002d88 0x40 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.map30_prgrom_flash_wr
0x08002b20 0x74 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002dc8 0x74 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.mmc4_prgrom_sop_flash_wr
0x08002b94 0x54 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002e3c 0x54 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.mmc3_prgrom_flash_wr
0x08002be8 0x50 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002e90 0x50 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.disc_push_exp0_prgrom_wr
0x08002c38 0x48 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002ee0 0x48 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.discrete_exp0_prgrom_wr
0x08002c80 0x58 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002f28 0x58 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.unrom_prgrom_flash_wr
0x08002cd8 0x64 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002f80 0x64 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.nrom_prgrom_flash_wr
0x08002d3c 0x44 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08002fe4 0x44 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.n64_latch_addr
0x08003028 0x50 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.pbje_scan
0x08002d80 0x10c C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08003078 0x10c C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.pbje_state_change
0x08002e8c 0x88 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08003184 0x88 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.jtag_init_pbje
0x08002f14 0xe0 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x0800320c 0xe0 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.jtag_run_pbje.part.0
0x08002ff4 0xb8 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x080032ec 0xb8 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.io_reset
0x080030ac 0x174 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.text.gba_rd 0x08003220 0x4c C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x080033a4 0x174 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.gba_rd 0x08003518 0x4c C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.write_page_verify
0x0800326c 0x5c C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08003564 0x5c C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.write_page
0x080032c8 0x34 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x080035c0 0x34 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.get_next_buff
0x080032fc 0x54 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x080035f4 0x54 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.mmc1_wr.constprop.12
0x08003350 0x22 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
*fill* 0x08003372 0x2 ff
0x08003648 0x22 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x0800366a 0x2 ff
.text.mmc1_chrrom_flash_wr
0x08003374 0x60 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x0800366c 0x60 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.mmc1_prgrom_flash_wr
0x080033d4 0x50 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x080036cc 0x50 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.swim_wotf
0x08003424 0xb4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x0800371c 0xb4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.swim_rotf
0x080034d8 0xac C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x080037d0 0xac C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.text.startup.main
0x08003584 0xae8 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x08003584 main
*fill* 0x0800406c 0x4 ff
.text 0x08004070 0x154 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
0x08004070 swim_xfr
.text 0x080041c4 0xa08 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
0x08004480 _Unwind_GetCFA
0x08004484 __gnu_Unwind_RaiseException
0x080044d8 __gnu_Unwind_ForcedUnwind
0x080044ec __gnu_Unwind_Resume
0x08004534 __gnu_Unwind_Resume_or_Rethrow
0x08004550 _Unwind_Complete
0x08004554 _Unwind_DeleteException
0x08004564 _Unwind_VRS_Get
0x080045ac _Unwind_VRS_Set
0x080045f4 __gnu_Unwind_Backtrace
0x08004944 __aeabi_unwind_cpp_pr0
0x08004950 __aeabi_unwind_cpp_pr1
0x0800495c __aeabi_unwind_cpp_pr2
0x08004968 _Unwind_VRS_Pop
.text 0x08004bcc 0x144 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(libunwind.o)
0x08004bcc __restore_core_regs
0x08004bcc restore_core_regs
0x08004bf8 __gnu_Unwind_Restore_VFP
0x08004bfc __gnu_Unwind_Save_VFP
0x08004c00 __gnu_Unwind_Restore_VFP_D
0x08004c04 __gnu_Unwind_Save_VFP_D
0x08004c08 __gnu_Unwind_Restore_VFP_D_16_to_31
0x08004c0c __gnu_Unwind_Save_VFP_D_16_to_31
0x08004c10 __gnu_Unwind_Restore_WMMXD
0x08004c14 __gnu_Unwind_Save_WMMXD
0x08004c18 __gnu_Unwind_Restore_WMMXC
0x08004c1c __gnu_Unwind_Save_WMMXC
0x08004c20 ___Unwind_RaiseException
0x08004c20 _Unwind_RaiseException
0x08004c50 _Unwind_Resume
0x08004c50 ___Unwind_Resume
0x08004c80 _Unwind_Resume_or_Rethrow
0x08004c80 ___Unwind_Resume_or_Rethrow
0x08004cb0 _Unwind_ForcedUnwind
0x08004cb0 ___Unwind_ForcedUnwind
0x08004ce0 ___Unwind_Backtrace
0x08004ce0 _Unwind_Backtrace
.text 0x08004d10 0x39c c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x08004d64 __gnu_unwind_execute
0x08005054 __gnu_unwind_frame
0x0800507c _Unwind_GetRegionStart
0x08005088 _Unwind_GetLanguageSpecificData
0x0800509c _Unwind_GetDataRelBase
0x080050a4 _Unwind_GetTextRelBase
.text.abort 0x080050ac 0x10 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o)
0x080050ac abort
.text.memcpy 0x080050bc 0x88 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-memcpy-stub.o)
0x080050bc memcpy
0x0800387c 0xb54 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x0800387c main
.text 0x080043d0 0x154 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
0x080043d0 swim_xfr
.text 0x08004524 0xa08 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
0x080047e0 _Unwind_GetCFA
0x080047e4 __gnu_Unwind_RaiseException
0x08004838 __gnu_Unwind_ForcedUnwind
0x0800484c __gnu_Unwind_Resume
0x08004894 __gnu_Unwind_Resume_or_Rethrow
0x080048b0 _Unwind_Complete
0x080048b4 _Unwind_DeleteException
0x080048c4 _Unwind_VRS_Get
0x0800490c _Unwind_VRS_Set
0x08004954 __gnu_Unwind_Backtrace
0x08004ca4 __aeabi_unwind_cpp_pr0
0x08004cb0 __aeabi_unwind_cpp_pr1
0x08004cbc __aeabi_unwind_cpp_pr2
0x08004cc8 _Unwind_VRS_Pop
.text 0x08004f2c 0x144 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(libunwind.o)
0x08004f2c __restore_core_regs
0x08004f2c restore_core_regs
0x08004f58 __gnu_Unwind_Restore_VFP
0x08004f5c __gnu_Unwind_Save_VFP
0x08004f60 __gnu_Unwind_Restore_VFP_D
0x08004f64 __gnu_Unwind_Save_VFP_D
0x08004f68 __gnu_Unwind_Restore_VFP_D_16_to_31
0x08004f6c __gnu_Unwind_Save_VFP_D_16_to_31
0x08004f70 __gnu_Unwind_Restore_WMMXD
0x08004f74 __gnu_Unwind_Save_WMMXD
0x08004f78 __gnu_Unwind_Restore_WMMXC
0x08004f7c __gnu_Unwind_Save_WMMXC
0x08004f80 ___Unwind_RaiseException
0x08004f80 _Unwind_RaiseException
0x08004fb0 _Unwind_Resume
0x08004fb0 ___Unwind_Resume
0x08004fe0 _Unwind_Resume_or_Rethrow
0x08004fe0 ___Unwind_Resume_or_Rethrow
0x08005010 _Unwind_ForcedUnwind
0x08005010 ___Unwind_ForcedUnwind
0x08005040 ___Unwind_Backtrace
0x08005040 _Unwind_Backtrace
.text 0x08005070 0x39c c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x080050c4 __gnu_unwind_execute
0x080053b4 __gnu_unwind_frame
0x080053dc _Unwind_GetRegionStart
0x080053e8 _Unwind_GetLanguageSpecificData
0x080053fc _Unwind_GetDataRelBase
0x08005404 _Unwind_GetTextRelBase
.text.abort 0x0800540c 0x10 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-abort.o)
0x0800540c abort
.text.memcpy 0x0800541c 0x88 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-memcpy-stub.o)
0x0800541c memcpy
.text._raise_r
0x08005144 0x5c c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o)
0x08005144 _raise_r
.text.raise 0x080051a0 0x14 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o)
0x080051a0 raise
.text._kill_r 0x080051b4 0x28 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o)
0x080051b4 _kill_r
0x080054a4 0x5c c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o)
0x080054a4 _raise_r
.text.raise 0x08005500 0x14 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signal.o)
0x08005500 raise
.text._kill_r 0x08005514 0x28 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o)
0x08005514 _kill_r
.text._getpid_r
0x080051dc 0x8 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o)
0x080051dc _getpid_r
.text._getpid 0x080051e4 0x10 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o)
0x080051e4 _getpid
.text._kill 0x080051f4 0x10 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(kill.o)
0x080051f4 _kill
.text._exit 0x08005204 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
0x08005204 _exit
0x0800553c 0x8 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-signalr.o)
0x0800553c _getpid_r
.text._getpid 0x08005544 0x10 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o)
0x08005544 _getpid
.text._kill 0x08005554 0x10 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(kill.o)
0x08005554 _kill
.text._exit 0x08005564 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(_exit.o)
0x08005564 _exit
*(.init)
.init 0x08005208 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o
0x08005208 _init
.init 0x08005568 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o
0x08005568 _init
*(.fini)
.fini 0x0800520c 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o
0x0800520c _fini
.fini 0x0800556c 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o
0x0800556c _fini
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend.o *crtend?.o) .ctors)
@ -701,42 +705,42 @@ LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eab
*(.rodata*)
*(.eh_frame*)
.glue_7 0x08005210 0x0
.glue_7 0x08005210 0x0 linker stubs
.glue_7 0x08005570 0x0
.glue_7 0x08005570 0x0 linker stubs
.glue_7t 0x08005210 0x0
.glue_7t 0x08005210 0x0 linker stubs
.glue_7t 0x08005570 0x0
.glue_7t 0x08005570 0x0 linker stubs
.vfp11_veneer 0x08005210 0x0
.vfp11_veneer 0x08005210 0x0 linker stubs
.vfp11_veneer 0x08005570 0x0
.vfp11_veneer 0x08005570 0x0 linker stubs
.v4_bx 0x08005210 0x0
.v4_bx 0x08005210 0x0 linker stubs
.v4_bx 0x08005570 0x0
.v4_bx 0x08005570 0x0 linker stubs
.iplt 0x08005210 0x0
.iplt 0x08005210 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.iplt 0x08005570 0x0
.iplt 0x08005570 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.ARM.extab 0x08005210 0x30
.ARM.extab 0x08005570 0x30
*(.ARM.extab* .gnu.linkonce.armextab.*)
.ARM.extab 0x08005210 0x24 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.ARM.extab 0x08005234 0xc c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x08005240 __exidx_start = .
.ARM.extab 0x08005570 0x24 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.ARM.extab 0x08005594 0xc c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x080055a0 __exidx_start = .
.ARM.exidx 0x08005240 0xd0
.ARM.exidx 0x080055a0 0xd0
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
.ARM.exidx 0x08005240 0x8 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.ARM.exidx 0x080055a0 0x8 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
0x10 (size before relaxing)
.ARM.exidx 0x08005248 0x98 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
.ARM.exidx 0x080055a8 0x98 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(unwind-arm.o)
0xd8 (size before relaxing)
.ARM.exidx 0x080052e0 0x30 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
.ARM.exidx 0x08005640 0x30 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m\libgcc.a(pr-support.o)
0x48 (size before relaxing)
0x08005310 __exidx_end = .
0x08005310 __etext = ALIGN (0x4)
0x08005670 __exidx_end = .
0x08005670 __etext = ALIGN (0x4)
.rel.dyn 0x08005310 0x0
.rel.iplt 0x08005310 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.rel.dyn 0x08005670 0x0
.rel.iplt 0x08005670 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.data 0x20000000 0x430 load address 0x08005310
.data 0x20000000 0x430 load address 0x08005670
0x20000000 __data_start__ = .
*(vtable)
*(.data*)
@ -764,75 +768,76 @@ LOAD c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eab
*(.fastrun)
0x20000430 __data_end__ = .
.igot.plt 0x20000430 0x0 load address 0x08005740
.igot.plt 0x20000430 0x0 C:\Users\paul\AppData\Local\Temp\ccUnJdk0.o
.igot.plt 0x20000430 0x0 load address 0x08005aa0
.igot.plt 0x20000430 0x0 C:\Users\paul\AppData\Local\Temp\ccwjSKJ8.o
.bss 0x20000430 0x308 load address 0x08005740
.bss 0x20000430 0x308 load address 0x08005aa0
0x20000430 . = ALIGN (0x4)
0x20000430 __bss_start__ = .
*(.bss*)
.bss.addr_ptr 0x20000430 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.addrh 0x20000434 0x2 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.addr_ptr 0x20000430 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.addrh 0x20000434 0x2 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.bank_table
0x20000436 0x2 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.buff0 0x20000438 0x14 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.buff1 0x2000044c 0x14 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.buff2 0x20000460 0x14 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.buff3 0x20000474 0x14 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x20000436 0x2 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.buff0 0x20000438 0x14 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.buff1 0x2000044c 0x14 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.buff2 0x20000460 0x14 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.buff3 0x20000474 0x14 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.cur_addr_hi
0x20000488 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x20000488 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000489 0x1
.bss.cur_addr_lo
0x2000048a 0x2 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.cur_bank 0x2000048c 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x2000048a 0x2 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.cur_bank 0x2000048c 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x2000048d 0x3
.bss.cur_buff 0x20000490 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.cur_buff 0x20000490 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.cur_usb_load_buff
0x20000494 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x20000494 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.incoming_bytes_remain
0x20000498 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x20000498 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000499 0x3
.bss.lfsr 0x2000049c 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.num_buff.5089
0x200004a0 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
*fill* 0x200004a1 0x3
.bss.lfsr 0x2000049c 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.n64_bank 0x200004a0 0x2 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.num_buff.5101
0x200004a2 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x200004a3 0x1
.bss.oper_info_struct
0x200004a4 0x20 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004a4 0x20 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.pbje_command
0x200004c4 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004c4 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.pbje_data
0x200004c5 0x20 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004c5 0x20 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.pbje_numclk
0x200004e5 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004e5 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.pbje_status
0x200004e6 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004e6 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.raw_bank_status
0x200004e7 0x10 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004e7 0x10 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x200004f7 0x1
.bss.raw_buffer16
0x200004f8 0x200 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200004f8 0x200 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.rv16.4756
0x200006f8 0x8 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.rv16.5009
0x20000700 0x8 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x200006f8 0x8 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.rv16.5021
0x20000700 0x8 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.stm_debug_disable
0x20000708 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x20000708 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000709 0x3
.bss.swim_base
0x2000070c 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.swim_pin 0x20000710 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x2000070c 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.swim_pin 0x20000710 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000711 0x3
.bss.tck_base 0x20000714 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tck_pin 0x20000718 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tck_base 0x20000714 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.tck_pin 0x20000718 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000719 0x3
.bss.tdi_base 0x2000071c 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tdi_pin 0x20000720 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tdi_base 0x2000071c 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.tdi_pin 0x20000720 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000721 0x3
.bss.tdo_base 0x20000724 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tdo_pin 0x20000728 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tdo_base 0x20000724 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.tdo_pin 0x20000728 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*fill* 0x20000729 0x3
.bss.tms_base 0x2000072c 0x4 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tms_pin 0x20000730 0x1 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.bss.tms_base 0x2000072c 0x4 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.bss.tms_pin 0x20000730 0x1 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
*(COMMON)
*fill* 0x20000731 0x3
COMMON 0x20000734 0x4 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libg.a(lib_a-reent.o)
@ -859,45 +864,45 @@ OUTPUT(build_stm/inlretro_stm.elf elf32-littlearm)
.ARM.attributes
0x00000000 0x1e c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/thumb/v6-m/crti.o
.ARM.attributes
0x0000001e 0x2f C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x0000001e 0x2f C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.ARM.attributes
0x0000004d 0x21 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
0x0000004d 0x21 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.comment 0x00000000 0x7f
.comment 0x00000000 0x7f C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.comment 0x00000000 0x7f C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x80 (size before relaxing)
.debug_info 0x00000000 0x51d1
.debug_info 0x00000000 0x51ab C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.debug_info 0x000051ab 0x26 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.debug_info 0x00000000 0x5499
.debug_info 0x00000000 0x5473 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.debug_info 0x00005473 0x26 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.debug_abbrev 0x00000000 0x69e
.debug_abbrev 0x00000000 0x68a C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.debug_abbrev 0x0000068a 0x14 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.debug_abbrev 0x00000000 0x6af
.debug_abbrev 0x00000000 0x69b C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.debug_abbrev 0x0000069b 0x14 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.debug_loc 0x00000000 0x51c7
.debug_loc 0x00000000 0x51c7 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.debug_loc 0x00000000 0x55ae
.debug_loc 0x00000000 0x55ae C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.debug_aranges 0x00000000 0x1e0
.debug_aranges 0x00000000 0x1f0
.debug_aranges
0x00000000 0x1c0 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x00000000 0x1d0 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.debug_aranges
0x000001c0 0x20 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
0x000001d0 0x20 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.debug_ranges 0x00000000 0xd18
.debug_ranges 0x00000000 0xd18 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.debug_ranges 0x00000000 0xdd8
.debug_ranges 0x00000000 0xdd8 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.debug_line 0x00000000 0x19ae
.debug_line 0x00000000 0x18bb C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.debug_line 0x000018bb 0xf3 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.debug_line 0x00000000 0x1b37
.debug_line 0x00000000 0x1a44 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.debug_line 0x00001a44 0xf3 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.debug_str 0x00000000 0x11c2
.debug_str 0x00000000 0x1161 C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
0x127e (size before relaxing)
.debug_str 0x00001161 0x61 C:\Users\paul\AppData\Local\Temp\ccENOwHW.o
.debug_str 0x00000000 0x122f
.debug_str 0x00000000 0x11ce C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
0x12eb (size before relaxing)
.debug_str 0x000011ce 0x61 C:\Users\paul\AppData\Local\Temp\ccobfpka.o
.debug_frame 0x00000000 0x59c
.debug_frame 0x00000000 0x59c C:\Users\paul\AppData\Local\Temp\ccQzBxIk.ltrans0.ltrans.o
.debug_frame 0x00000000 0x5d8
.debug_frame 0x00000000 0x5d8 C:\Users\paul\AppData\Local\Temp\cc7Ghupa.ltrans0.ltrans.o
.stabstr 0x00000000 0x76
.stabstr 0x00000000 0x76 c:/arm/gcc-arm-none-eabi-7-2018-q2-update-win32/bin/../lib/gcc/arm-none-eabi/7.3.1/../../../../arm-none-eabi/lib/thumb/v6-m\libnosys.a(getpid.o)

33
firmware/source/dump.c
View File

@ -85,10 +85,41 @@ uint8_t dump_buff( buffer *buff ) {
case GBA_ROM_PAGE:
//address must have already been latched
//we're only telling page_rd the number of bytes to read, and where to put it
buff->cur_byte = gba_page_rd( buff->data, buff->last_idx );
// takes 16bit pointer, 127 / 2 = 63.5 -> 63 so it works
buff->cur_byte = gba_page_rd( (uint16_t*)buff->data, (buff->last_idx>>1) );
//buff->cur_byte = gba_page_rd( buff->data, buff->last_idx );
break;
#endif
#ifdef SEGA_CONN
case GENESIS_ROM_PAGE0:
//mapper byte specifies Genesis CPU A15-8
addrH |= (buff->mapper); //no shift needed
buff->cur_byte = genesis_page_rd( buff->data, addrH, buff->id,
//id contains MSb of page when <256B buffer
buff->last_idx);
break;
case GENESIS_ROM_PAGE1:
//mapper byte specifies Genesis CPU A15-8
addrH |= (buff->mapper); //no shift needed
buff->cur_byte = genesis_page_rd( buff->data, addrH+0x0100, buff->id,
//id contains MSb of page when <256B buffer
buff->last_idx);
break;
#endif
#ifdef N64_CONN
case N64_ROM_PAGE:
//mapper byte specifies SNES CPU A15-8
//uint8_t addrH = buff->page_num; //A15:8 while accessing page
// addrH |= (buff->mapper); //no shift needed
buff->cur_byte = n64_page_rd( buff->data, addrH, buff->id,
//id contains MSb of page when <256B buffer
buff->last_idx);
break;
#endif
#ifdef NES_CONN
case PRGROM:
addrH |= 0x80; //$8000

11
firmware/source/gba.c
View File

@ -32,6 +32,8 @@ uint8_t gba_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
//resist temptation to make these 16bit indexes
//will break rule of accessing usb_buff in half word aligned access
//would have to use RD1-RD2 for 16bit aligned access..
//Actually.. that's not true. return & RD_LEN are index 0-1, so RD0-1 would be index 2-3
//so it should be half word aligned..
#define BYTE_LEN 1
#define HWORD_LEN 2
@ -117,8 +119,8 @@ uint16_t gba_rd()
}
//can only read 255 bytes, len can't be 255 else it would create infinite loop
//TODO get a 16bit data pointer
uint8_t gba_page_rd( uint8_t *data, uint8_t len)
// I think the byte read version is actually slightly faster...?
uint8_t gba_page_rd( uint16_t *data, uint8_t len)
{
uint8_t i;
uint16_t read;
@ -131,13 +133,14 @@ uint8_t gba_page_rd( uint8_t *data, uint8_t len)
read = gba_rd();
//store lower byte little endian
//now stores entire 16bit read at once
data[i] = read;
//upper byte
i++;
//i++;
//store upper byte
data[i] = read>>8;
//data[i] = read>>8;
}
//return index of last byte read

2
firmware/source/gba.h
View File

@ -9,6 +9,6 @@ uint8_t gba_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
uint16_t gba_rd();
void gba_latch_addr( uint16_t addr_lo, uint8_t addr_hi);
uint8_t gba_page_rd( uint8_t *data, uint8_t len);
uint8_t gba_page_rd( uint16_t *data, uint8_t len);
#endif

176
firmware/source/io.c
View File

@ -54,7 +54,7 @@ uint8_t io_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rd
case SEGA_INIT: sega_init(); break;
#endif
#ifdef N64_CONN
// case N64_INIT: n64_init(); break;
case N64_INIT: n64_init(); break;
#endif
case SWIM_INIT:
return swim_init(operand); break;
@ -370,39 +370,177 @@ void sega_init()
io_reset();
//enable control outputs and disable memories
//ROM
// CONSOLE OUTPUTS:
// #C_CE B17 CPU access $00_0000 - 03_FFFF 4MByte cart space
// address decode depends on #CART
// cart normally drives low (00-03),
// but if driven high (like CD sram cart) decodes to $04_0000 - 07_FFFF
ROMSEL_OP();
ROMSEL_HI(); // #C_CE
ROMSEL_HI();
// #C_OE B16 CPU access $00_0000 - 0D_FFFF entire 68k map except bank 0E-FF (64K RAM)
CSRD_OP();
CSRD_HI(); // #C_OE
CSWR_OP();
CSWR_HI(); // #UDSW
PRGRW_OP();
PRGRW_HI(); // #LDSW
CSRD_HI();
//disable SRAM and put cart in PLAY mode
EXP0_HI();
// #AS B18 CPU access entire memory map, indicating address bus valid
// TODO create another macro over the top of this..
GBP_OP();
GBP_HI();
// #LO_MEM B26 CPU access $00_0000 - 07_FFFF 8MByte cart space
// TODO FF2
// #RESET (aka vRES) B27 resets cart logic, stays low in SMS mode
EXP0_OP();
//if SWIM is active, EXP0 must be set to pullup prior to SWIM transfers
EXP0_HI();
//other control pins are inputs or unused, leave as IP pullup from reset
// #LDSW B28 CPU D0-7 data strobe
PRGRW_OP();
PRGRW_HI();
// #UDSW B29 CPU D8-15 data strobe
CSWR_OP();
CSWR_HI();
// #TIME B31 CPU access $A1_3000 - A1_30FF "SSF2 mapper" uses this to decode mapper register writes
// TODO FF7
// CLK B19 7Mhz clock?
// HS_CLK B15 13/53Mhz clock?
// TODO PA8 both clock pins are wired to this mcu pin
// #CAS B21 when CPU is halted, pulses at 60Khz probably refreshing some DRAM..
// mcu ties with CPU A1 (address)
//
// VIDEO B12 non-NTSC EGA?
// mcu ties with CPU A3 (address)
//
// Vsync B13 60Khz?
// mcu ties with CPU A2 (address)
//
// Hsync B14 16Khz?
// mcu ties with AFL (for A17+ flipflop clk/oen)
// CONSOLE INPUTS:
// #H_RESET B2 (aka nMRES) console input, causes a hard reset, like what happens at power up
// enables the OS rom which verifies "SEGA" present
//
// #S_RESET B30 (aka SEL0) console input, causes a soft reset, like pressing reset on the console
// SMS power adapter grounds this pin
// TODO SWCLK PA14
//
// #CART_IN B32 controls the address mapping of #C_CE, most carts ground this pin, CD ram adapter ties VCC
// TODO PD2 (COUT)
//
// SOUND_LEFT B1 cart audio output
// TODO ADC IN PA4 (AUDL)
//
// SOUND_RIGHT B3 cart audio output
// TODO ADC IN PA5 (AUDR)
// CONSOLE BIDIR:
// #DTACK B20 bidirectional indicates end of data transfer, think the CPU stalls till memory drives
// for non-cart space (wired to mcu pin PA13 (SWDIO)
//now meet conditions to call other macros
//setup address $00_0000
ADDR_ENABLE(); //A1-16
//A17-18, #LO_MEM, A20-23, #TIME
//behind AFL
FFADDR_ENABLE();
// 0b1000_0100 #LO_MEM & #TIME high
#define LOMEM_TIME_MSK 0x84 //TODO put this in pinport?
FFADDR_SET(LOMEM_TIME_MSK); //corrupts A1-16
//A1-16
ADDR_SET(0x0000);
//A19 (pin B7) SMS power adapter drives this pin for #IORQ
IRQ_OP();
IRQ_LO(); //A19 low
//memories are now disabled Data bus should be clear
// SEGA D0-7
DATA_ENABLE();
DATA_IP_PU();
//now meet conditions to call other macros
//setup address $0000
ADDR_ENABLE();
ADDR_SET(0x0000);
//setup HIGH ADDR with bank $00
//SEGA D8-15
HADDR_ENABLE();
HADDR_SET(0x00);
HADDR_IP();
HADDR_PU();
}
#endif
//N64 cartridge interfacing setup
//set outputs as required
//latch address of $0000
//disable cart memories
#ifdef N64_CONN
void n64_init()
{
//start with a reset
//expecting user to do this but just to be sure
//this also sets power to 3v
io_reset();
//enable control outputs and disable memories
//ROM-RAM
// ALE_L
ALE_L_OP(); //ROMSEL_OP();
ALE_L_HI(); //ROMSEL_HI();
// ALE_H
ALE_H_OP(); //PRGRW_OP();
ALE_H_OP(); //PRGRW_HI();
// RD
CSRD_OP();
CSRD_HI();
// WR
CSWR_OP();
CSWR_HI();
// COLD #RESET
EXP0_OP();
EXP0_HI();
//TODO
//1.6Mhz clock -> D4 (PB12)
//S_DAT -> D5 (PB13)
//CIC_D2 -> D14 (PA9)
//JTAG_CLK_44 -> D15 (PA10)
//BLANK 14 & 39 -> D9/D10 (PB3/4)
//CIC_D1 -> D11 (PB5)
//VIDEO_CLK_46 -> D12 (PB6)
//OS_EVENT -> D13 (PB7)
//
// SOUND_LEFT
// TODO ADC IN PA4 (AUDL)
//
// SOUND_RIGHT
// TODO ADC IN PA5 (AUDR)
//AD0-15 leave as input pullup
ADDR_ENABLE(); //turns on GPIO block & sets to output
ADDR_IP(); //ad0-15 input
ADDR_PU(); //ad0-15 pullup
ADDR_SET(0x0000); //output set to zero, but won't take effect until outputed
}
#endif
//Initialization of SWIM "single wire interface module" communications
//the SWIM pin depends on INL board design.
//dict call must provide the "swim_lane"

1
firmware/source/io.h
View File

@ -15,6 +15,7 @@ void snes_init();
void gameboy_init();
void gba_init();
void sega_init();
void n64_init();
uint8_t swim_init(uint8_t opcode);
uint8_t jtag_init(uint8_t opcode);
uint8_t exp0_pullup_test();

135
firmware/source/n64.c
View File

@ -3,6 +3,8 @@
//only need this file if connector is present on the device
#ifdef N64_CONN
uint16_t n64_bank;
//=================================================================================================
//
// N64 operations
@ -32,15 +34,39 @@ uint8_t n64_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
switch (opcode) {
// //no return value:
case N64_WR:
n64_wr( operand, miscdata );
// TODO case N64_WR:
// n64_wr( operand, miscdata );
// break;
case N64_SET_BANK:
n64_bank = operand;
break;
case N64_LATCH_ADDR:
//operand A0-15, use SET_ADDR_HI above to set upper address (aka "bank")
n64_latch_addr( operand );
break;
case N64_RELEASE_BUS:
//latch addr will do this for us so maybe not needed..
ALE_H_HI();
NOP();
NOP();
NOP();
NOP();
NOP();
ALE_L_HI();
break;
//8bit return values:
case N64_RD:
rdata[RD_LEN] = BYTE_LEN;
rdata[RD0] = n64_rd( operand );
rdata[RD_LEN] = HWORD_LEN;
//can use operand as a variable
operand = n64_rd();
rdata[RD0] = operand;
rdata[RD1] = operand>>8;
break;
default:
//macro doesn't exist
return ERR_UNKN_N64_OPCODE;
@ -50,16 +76,105 @@ uint8_t n64_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
}
uint8_t n64_rd( uint16_t addr )
{
return 0xAA;
}
void n64_wr( uint16_t addr, uint8_t data )
{
return;
}
//latches AD1-15, leaves ALE_L/H low for subsequent accesses
//RD shouldn't be left low, assuming high
void n64_latch_addr( uint16_t addr_lo )
{
//store address so other functions can keep track of incrementing
//cur_addr_lo = addr_lo;
//set ALE high incase it wasn't
ALE_H_HI();
NOP();
NOP();
NOP();
NOP();
NOP();
NOP();
ALE_L_HI();
//set addr & data bus to output
ADDR_OP();
//IDK if the order ALE_H/L matters, docs have H first
ADDR_SET(n64_bank);
NOP();
ALE_H_LO();
//latch low address A0 is effectively ignored
ADDR_SET(addr_lo);
NOP();
ALE_L_LO();
//leave AD0-15 as input for subsequent access
ADDR_IP();
return;
}
//address must already have been latched
//will increment address variables and A16-23
//ready to read next byte
uint16_t n64_rd()
{
uint16_t read;
//if( cur_addr_lo == 0xFFFF ) {
// //going to have a roll over when incrementing
// cur_addr_hi++;
// //don't output it till this access is done though
//}
CSRD_LO();
//cur_addr_lo++; //increment to next byte that will be read
NOP();
NOP();
read = ADDR_VAL;
CSRD_HI();
return read;
}
//can only read 255 bytes, len can't be 255 else it would create infinite loop
// I think the byte read version is actually slightly faster...?
uint8_t n64_page_rd( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len )
{
uint16_t read;
uint8_t i;
n64_latch_addr( addrH<<8 | first );
//now can call n64_rd to get 16bits of data
for( i=0; i<=len; i++ ) {
//usbPoll(); //Call usbdrv.h usb polling while waiting for data
//read 16bits
read = n64_rd();
//store lower byte little endian
//now stores entire 16bit read at once
data[i] = read>>8;
//upper byte
i++;
//store upper byte
data[i] = read;
}
//return index of last byte read
return i;
}
#endif //N64_CONN

5
firmware/source/n64.h
View File

@ -7,7 +7,10 @@
uint8_t n64_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata );
uint8_t n64_rd( uint16_t addr );
uint16_t n64_rd();
void n64_wr( uint16_t addr, uint8_t data );
void n64_latch_addr( uint16_t addr_lo );
uint8_t n64_page_rd( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len );
#endif

20
firmware/source/pinport.c
View File

@ -391,6 +391,12 @@ uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_
case ADDR_IP_: ADDR_IP(); break;
case ADDR_OP_: ADDR_OP(); break;
case ADDR_SET_: ADDR_SET(operand); break;
#ifdef ADDR_VAL
case ADDR_RD_: rdata[RD_LEN] = 1;
rdata[RD0] = ADDR_VAL;
rdata[RD1] = ADDR_VAL>>8; break;
#endif
//============================
//EXP PORT 8bit ACCESS (bits1-8)
@ -401,6 +407,7 @@ uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_
case EXP_DISABLE_: EXP_DISABLE(); break;
case EXP_SET_: EXP_SET(operand); break;
//============================
//HIGH ADDR PORT 8bit WIDE ACCESS
//opcode: type of operation
@ -412,6 +419,19 @@ uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_
case HADDR_SET_: HADDR_SET(operand); break;
#endif
//============================
//FLIPFLOP ADDR PORT 8bit WIDE ACCESS
//opcode: type of operation
//operand: value to place on bus
//============================
#ifdef SEGA_CONN
case FFADDR_ENABLE_: FFADDR_ENABLE(); break;
case FFADDR_DISABLE_: FFADDR_DISABLE(); break;
case FFADDR_SET_: FFADDR_SET(operand); break;
#endif
default:
//macro doesn't exist or isn't on this PCB version
return ERR_UNKN_PP_OPCODE;

10
firmware/source/pinport.h
View File

@ -31,6 +31,11 @@ uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_
#define ROMSEL_LO() CTL_SET_LO(ROMSELbank, ROMSEL)
#define ROMSEL_HI() CTL_SET_HI(ROMSELbank, ROMSEL)
#define ROMSEL_RD(val) CTL_RD(ROMSELbank, ROMSEL, val)
// same pin: N64 ALE_L
#define ALE_L_OP() CTL_OP(ROMSELbank, ROMSEL)
#define ALE_L_IP_PU() CTL_IP_PU(ROMSELbank, ROMSEL)
#define ALE_L_LO() CTL_SET_LO(ROMSELbank, ROMSEL)
#define ALE_L_HI() CTL_SET_HI(ROMSELbank, ROMSEL)
// PC2 "PRGRW"
#define PRGRW_IP_PU() CTL_IP_PU(PRGRWbank, PRGRW)
@ -39,6 +44,11 @@ uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_
#define PRGRW_LO() CTL_SET_LO(PRGRWbank, PRGRW)
#define PRGRW_HI() CTL_SET_HI(PRGRWbank, PRGRW)
#define PRGRW_RD(val) CTL_RD(PRGRWbank, PRGRW, val)
// same pin: N64 ALE_H
#define ALE_H_IP_PU() CTL_IP_PU(PRGRWbank, PRGRW)
#define ALE_H_OP() CTL_OP(PRGRWbank, PRGRW)
#define ALE_H_LO() CTL_SET_LO(PRGRWbank, PRGRW)
#define ALE_H_HI() CTL_SET_HI(PRGRWbank, PRGRW)
// PC3 "FREE"
#ifndef C3nodef

43
firmware/source/pinport_al.h
View File

@ -1165,8 +1165,9 @@ void software_AXL_CLK();
//Appears to be working for setting A10, but not A11 reguardless of order of execution..
//TODO really these macros should be making byte writes to the registers, not 16bit RMW
#define ADDR_SET(hword) Abank->ODR = hword
#define ADDR_RD(hword) hword = Abank->IDR
#define ADDR_VAL (Abank->IDR)
#define ADDR_CUR (Abank->ODR) //can use this to determine current address
#define ADDR_RD(hword) hword = Abank->IDR //can use this as a function ADDR_RD(data)
#define ADDR_VAL (Abank->IDR) //can use this to assign: data = ADDR_VAL
#define ADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_ADDR
#define ADDR_ENABLE() ADDR_EN_CLK(); ADDR_OP()
@ -1216,6 +1217,36 @@ void software_AXL_CLK();
#endif //AVR_KAZZO
// ---------------------------------------------------------------------------------------
// FLIPFLOP ADDR PORT 8bit
//
// This port is present on devices with sega connectors, and SNES if supports EXP pins
// It's behind the 8x Flipflop to give access to Sega A17-18, #AS, A20-23, #TIME
// SNES doesn't connect to FF0-3, but FF4-7 connect to /PARD, /PAWR, REFRESH, /WRAMSEL
// Directionality: All pins are forced output
// Driver: All pins are push-pull
// Write/Output: Byte access only, no bit accesses
// Read/Input: Not supported
//
// ---------------------------------------------------------------------------------------
#if defined(STM_INL6) || defined(STM_INL6_PROTO)
//These are behind the AFL flipflop similar to how the STM_NES has A8-15 behind AHL flipflop
//But the Flipflop's inputs are AD0-7
#define FFADDR_ENABLE() CTL_OP(AFLbank, AFL); CTL_SET_LO(AFLbank, AFL)
#define FFADDR_DISABLE() CTL_IP_PU(AFLbank, AFL);
//FFADDR must already be enabled
#define AFL_CLK() CTL_SET_HI(AFLbank, AFL); CTL_SET_LO(AFLbank, AFL)
//assumes A0-7 are enabled & outputs, corrupts AD0-15 (sega A1-16), AFL must be enabled & low/clocked
#define FFADDR_SET(high) ADDR_SET(high); AFL_CLK();
#endif //STM_INL6
// ---------------------------------------------------------------------------------------
// EXPANSION PORT 8bit pins #1-8
//
@ -1399,6 +1430,8 @@ void software_AXL_CLK();
#define HADDR_SET(val) A16_21bank->ODR = ((A16_21bank->ODR&0x03FF) | (val<<10 & 0xFC00)); A22_23bank->ODR = ((A22_23bank->ODR & 0xF9FF) | (val<<3 & 0x0600))
#define HADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_HADDR
#define HADDR_ENABLE() HADDR_EN_CLK(); HADDR_OP()
#define HADDR_DISABLE() HADDR_PU(); HADDR_IP()
@ -1418,6 +1451,12 @@ void software_AXL_CLK();
#define HADDR_SET(val) A16_21bank->ODR = ((A16_21bank->ODR&0xFF03) | (val<<2 & 0x00FC)); A22_23bank->ODR = ((A22_23bank->ODR & 0xF9FF) | (val<<3 & 0x0600))
//sega reading D8-15
//D8-13 are on PB2-7
//D14-15 are on PA9-10
#define HDATA_VAL (((A16_21bank->IDR)&0x00FC)>>2) | (((A22_23bank->IDR)&0x0600) >>3)
//can use this to assign: data = HDATA_VAL
#define HADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_HADDR
#define HADDR_ENABLE() HADDR_EN_CLK(); HADDR_OP()
#define HADDR_DISABLE() HADDR_PU(); HADDR_IP()

87
firmware/source/sega.c
View File

@ -29,6 +29,8 @@ uint8_t sega_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *
#define BYTE_LEN 1
#define HWORD_LEN 2
uint16_t temp;
switch (opcode) {
// //no return value:
@ -36,6 +38,21 @@ uint8_t sega_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *
sega_wr( operand, miscdata );
break;
case SET_BANK:
temp = ADDR_CUR; //this will get stomped
#define LOMEM_TIME_MASK 0x84
//A17-18, 20-23
FFADDR_SET( operand | LOMEM_TIME_MASK ); //TODO decode #TIME & LO_MEM
ADDR_SET(temp); //restore A1-16
#define SEGA_A19_MASK 0x04
//A19
if ( operand & SEGA_A19_MASK ) {
IRQ_HI();
} else {
IRQ_LO();
}
break;
//8bit return values:
case SEGA_RD:
rdata[RD_LEN] = BYTE_LEN;
@ -62,4 +79,74 @@ void sega_wr( uint16_t addr, uint8_t data )
}
/* Desc:SNES ROM Page Read with optional USB polling
* /ROMSEL based on romsel arg, EXP0/RESET unaffected
* if poll is true calls usbdrv.h usbPoll fuction
* this is needed to keep from timing out when double buffering usb data
* Pre: snes_init() setup of io pins
* num_bytes can't exceed 256B page boundary
* Post:address left on bus
* data bus left clear
* data buffer filled starting at first to last
* Rtn: Index of last byte read
*/
uint8_t genesis_page_rd( uint8_t *data, uint16_t addrH, uint8_t first, uint8_t len )
{
uint8_t i;
uint16_t address = first>>1; //shift because there is no A0
//address = ((addrH<<8) | first)>>1; //shift because there is no A0
address = (addrH<<7) | address; //shift because there is no A0
//set address
//ADDRH(addrH);
ADDRH(address>>8);
//set #C_CE
ROMSEL_LO();
//set #C_OE
CSRD_LO();
first = address;
//set lower address bits
ADDRL(first); //doing this prior to entry and right after latching
//gives longest delay between address out and latching data
for( i=0; i<=len; i++ ) {
//gameboy needed some extra NOPS
NOP();
NOP();
NOP();
NOP();
NOP();
NOP();
NOP();
NOP();
//latch data high byte
data[i] = HDATA_VAL;
i++;
//latch data low byte
DATA_RD(data[i]);
//set lower address bits
//ADDRL(++first); THIS broke things, on stm adapter because macro expands it twice!
first++;
ADDRL(first);
}
//return bus to default
CSRD_HI();
ROMSEL_HI();
//return index of last byte read
return i;
}
#endif //SEGA_CONN

3
firmware/source/sega.h
View File

@ -5,9 +5,12 @@
#include "shared_dictionaries.h"
#include "shared_errors.h"
uint8_t sega_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata );
uint8_t sega_rd( uint16_t addr );
void sega_wr( uint16_t addr, uint8_t data );
uint8_t genesis_page_rd( uint8_t *data, uint16_t addrH, uint8_t first, uint8_t len );
#endif

4
host/scripts/gba/basic.lua
View File

@ -121,7 +121,7 @@ local function process(process_opts, console_opts)
--dump cart into file
time.start()
dump_rom(file, rom_size, false)
time.report(rom_size_KB)
time.report(rom_size)
--close file
assert(file:close())
@ -160,7 +160,7 @@ local function process(process_opts, console_opts)
--dump cart into file
time.start()
dump_rom(file, rom_size, false)
time.report(rom_size_KB)
time.report(rom_size)
--close file
assert(file:close())

13
host/scripts/inlretro.lua
View File

@ -92,6 +92,12 @@ function main ()
--GBA
--local curcart = require "scripts.gba.basic"
--SEGA GENESIS
--local curcart = require "scripts.sega.genesis_v1"
--N64
--local curcart = require "scripts.n64.basic"
-- =====================================================
-- USERS: set cart_console to the to point to the mapper script you would like to use here.
@ -111,7 +117,7 @@ function main ()
-- will be ignored by mappers that don't support RAM.
-- =====================================================
local process_opts = {
test = true,
test = false,
read = true,
erase = false,
program = false,
@ -131,6 +137,7 @@ function main ()
local console_opts = {
mirror = nil, -- Only used by latest INL discrete flash boards, set to "H" or "V" to change board mirroring
prg_rom_size_kb = 32, -- Size of NES PRG-ROM in KByte
--prg_rom_size_kb = 8*1024, -- 8MByte ROM size example
chr_rom_size_kb = 8, -- Size of NES CHR-ROM in KByte
wram_size_kb = 0, -- Size of NES PRG-RAM/WRAM in KByte
}
@ -207,11 +214,14 @@ function main ()
elseif cart_console == "SEGA" then
curcart.process(process_opts, console_opts)
--always end with and gpio reset incase the script didn't
dict.io("IO_RESET")
elseif cart_console == "N64" then
curcart.process(process_opts, console_opts)
--always end with and gpio reset incase the script didn't
dict.io("IO_RESET")
@ -250,6 +260,7 @@ function main ()
elseif cart_console == "SMS" then
curcart.process(process_opts, console_opts)
--always end with and gpio reset incase the script didn't
dict.io("IO_RESET")
end

203
host/scripts/n64/basic.lua Normal file
View File

@ -0,0 +1,203 @@
-- create the module's table
local genesis_v1 = {}
-- import required modules
local dict = require "scripts.app.dict"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
local help = require "scripts.app.help"
-- file constants
-- local functions
--dump the SNES ROM starting at the provided bank
--/ROMSEL is always low for this dump
local function dump_rom( file, rom_size_KB, debug )
local KB_per_bank = 64 --AD0-15 = 64K address space, A0 ignored so 1Byte per address!
local addr_base = 0x0000 -- control signals are manually controlled
local bank_base = 0x1000 --N64 roms start at address 0x1000_0000
local num_reads = rom_size_KB / KB_per_bank
local read_count = 0
-- dict.n64("N64_SET_BANK", bank_base + 0)
-- dict.n64("N64_LATCH_ADDR", 0x0000)
-- print("read: ", help.hex(dict.n64("N64_RD")))
-- print("read: ", help.hex(dict.n64("N64_RD")))
-- dict.n64("N64_SET_BANK", bank_base + 0)
-- dict.n64("N64_LATCH_ADDR", 0x0000)
-- dump.dumptofile( file, KB_per_bank, addr_base, "N64_ROM_PAGE", false )
-- dict.n64("N64_RELEASE_BUS")
while ( read_count < num_reads ) do
if debug then print( "dump ROM part ", read_count, " of ", num_reads) end
if (read_count %8 == 0) then
print("dumping ROM bank: ", read_count, " of ", num_reads-1)
end
--select desired bank
dict.n64("N64_SET_BANK", (bank_base+read_count))
--dump a 64KByte chunk of rom
dump.dumptofile( file, KB_per_bank, addr_base, "N64_ROM_PAGE", false )
--prob don't need this till done..
dict.n64("N64_RELEASE_BUS")
read_count = read_count + 1
end
dict.n64("N64_RELEASE_BUS")
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process(process_opts, console_opts)
local test = process_opts["test"]
local read = process_opts["read"]
local erase = process_opts["erase"]
local program = process_opts["program"]
local verify = process_opts["verify"]
local dumpfile = process_opts["dump_filename"]
local flashfile = process_opts["flash_filename"]
local verifyfile = process_opts["verify_filename"]
local rv = nil
local file
local rom_size = console_opts["prg_rom_size_kb"]
local wram_size = console_opts["wram_size_kb"]
local mirror = console_opts["mirror"]
--initialize device i/o for N64
dict.io("IO_RESET")
dict.io("N64_INIT")
--test cart by reading manf/prod ID
if test then
-- print("Testing SNES board");
--
-- --SNES detect HiROM or LoROM & RAM
--
-- --SNES detect if able to read flash ID's
-- if not rom_manf_id(true) then
-- print("ERROR unable to read flash ID")
-- return
-- end
end
--dump the ram to file
if dumpram then
-- print("\nDumping SAVE RAM...")
--
-- --may have to verify /RESET is high to enable SRAM
--
-- file = assert(io.open(ramdumpfile, "wb"))
--
-- --dump cart into file
-- dump_ram(file, rambank, ram_size, snes_mapping, true)
--
-- --may disable SRAM by placing /RESET low
--
-- --close file
-- assert(file:close())
--
-- print("DONE Dumping SAVE RAM")
end
--dump the cart to dumpfile
if read then
print("\nDumping N64 ROM...")
file = assert(io.open(dumpfile, "wb"))
--dump cart into file
dump_rom(file, rom_size, false)
--close file
assert(file:close())
print("DONE Dumping N64 ROM")
end
--erase the cart
if erase then
-- erase_flash()
end
--write to wram on the cart
if writeram then
-- print("\nWritting to SAVE RAM...")
--
-- file = assert(io.open(ramwritefile, "rb"))
--
-- --flash.write_file( file, ram_size, "NOVAR", "PRGRAM", false )
-- --flash.write_file( file, ram_size, "LOROM_3VOLT", "SNESROM", false )
-- wr_ram(file, rambank, ram_size, snes_mapping, true)
--
-- --close file
-- assert(file:close())
--
-- print("DONE Writting SAVE RAM")
end
--program flashfile to the cart
if program then
-- --open file
-- file = assert(io.open(flashfile, "rb"))
-- --determine if auto-doubling, deinterleaving, etc,
-- --needs done to make board compatible with rom
--
-- --flash cart
-- flash_rom(file, rom_size, snes_mapping, true)
--
-- --close file
-- assert(file:close())
end
--verify flashfile is on the cart
if verify then
-- print("\nPost dumping SNES ROM...")
-- --for now let's just dump the file and verify manually
--
-- file = assert(io.open(verifyfile, "wb"))
--
-- --dump cart into file
-- dump_rom(file, rom_size, false)
--
-- --close file
-- assert(file:close())
-- print("DONE Post dumping SNES ROM")
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
genesis_v1.process = process
-- return the module's table
return genesis_v1

188
host/scripts/sega/genesis_v1.lua Normal file
View File

@ -0,0 +1,188 @@
-- create the module's table
local genesis_v1 = {}
-- import required modules
local dict = require "scripts.app.dict"
local dump = require "scripts.app.dump"
local flash = require "scripts.app.flash"
local snes = require "scripts.app.snes"
local apperase = require "scripts.app.erase"
-- file constants
-- local functions
--dump the SNES ROM starting at the provided bank
--/ROMSEL is always low for this dump
local function dump_rom( file, rom_size_KB, debug )
local KB_per_bank = 128 -- A1-16 = 64K address space, 2Bytes per address
local addr_base = 0x0000 -- control signals are manually controlled
local num_reads = rom_size_KB / KB_per_bank
local read_count = 0
while ( read_count < num_reads ) do
if debug then print( "dump ROM part ", read_count, " of ", num_reads) end
if (read_count %8 == 0) then
print("dumping ROM bank: ", read_count, " of ", num_reads-1)
end
--select desired bank
dict.sega("SET_BANK", read_count)
dump.dumptofile( file, KB_per_bank/2, addr_base, "GENESIS_ROM_PAGE0", false )
dump.dumptofile( file, KB_per_bank/2, addr_base, "GENESIS_ROM_PAGE1", false )
read_count = read_count + 1
end
end
--Cart should be in reset state upon calling this function
--this function processes all user requests for this specific board/mapper
local function process(process_opts, console_opts)
local test = process_opts["test"]
local read = process_opts["read"]
local erase = process_opts["erase"]
local program = process_opts["program"]
local verify = process_opts["verify"]
local dumpfile = process_opts["dump_filename"]
local flashfile = process_opts["flash_filename"]
local verifyfile = process_opts["verify_filename"]
local rv = nil
local file
local rom_size = console_opts["prg_rom_size_kb"]
local wram_size = console_opts["wram_size_kb"]
local mirror = console_opts["mirror"]
--initialize device i/o for SEGA
dict.io("IO_RESET")
dict.io("SEGA_INIT")
--test cart by reading manf/prod ID
if test then
-- print("Testing SNES board");
--
-- --SNES detect HiROM or LoROM & RAM
--
-- --SNES detect if able to read flash ID's
-- if not rom_manf_id(true) then
-- print("ERROR unable to read flash ID")
-- return
-- end
end
--dump the ram to file
if dumpram then
-- print("\nDumping SAVE RAM...")
--
-- --may have to verify /RESET is high to enable SRAM
--
-- file = assert(io.open(ramdumpfile, "wb"))
--
-- --dump cart into file
-- dump_ram(file, rambank, ram_size, snes_mapping, true)
--
-- --may disable SRAM by placing /RESET low
--
-- --close file
-- assert(file:close())
--
-- print("DONE Dumping SAVE RAM")
end
--dump the cart to dumpfile
if read then
print("\nDumping SEGA ROM...")
file = assert(io.open(dumpfile, "wb"))
--dump cart into file
dump_rom(file, rom_size, true)
--close file
assert(file:close())
print("DONE Dumping SEGA ROM")
end
--erase the cart
if erase then
-- erase_flash()
end
--write to wram on the cart
if writeram then
-- print("\nWritting to SAVE RAM...")
--
-- file = assert(io.open(ramwritefile, "rb"))
--
-- --flash.write_file( file, ram_size, "NOVAR", "PRGRAM", false )
-- --flash.write_file( file, ram_size, "LOROM_3VOLT", "SNESROM", false )
-- wr_ram(file, rambank, ram_size, snes_mapping, true)
--
-- --close file
-- assert(file:close())
--
-- print("DONE Writting SAVE RAM")
end
--program flashfile to the cart
if program then
-- --open file
-- file = assert(io.open(flashfile, "rb"))
-- --determine if auto-doubling, deinterleaving, etc,
-- --needs done to make board compatible with rom
--
-- --flash cart
-- flash_rom(file, rom_size, snes_mapping, true)
--
-- --close file
-- assert(file:close())
end
--verify flashfile is on the cart
if verify then
-- print("\nPost dumping SNES ROM...")
-- --for now let's just dump the file and verify manually
--
-- file = assert(io.open(verifyfile, "wb"))
--
-- --dump cart into file
-- dump_rom(file, rom_size, true)
--
-- --close file
-- assert(file:close())
-- print("DONE Post dumping SNES ROM")
end
dict.io("IO_RESET")
end
-- global variables so other modules can use them
-- call functions desired to run when script is called/imported
-- functions other modules are able to call
genesis_v1.process = process
-- return the module's table
return genesis_v1

4
shared/shared_dict_buffer.h
View File

@ -122,6 +122,10 @@
#define SNESSYS_PAGE 0x25 //mapper byte specifies A15-8 ROMSEL high
#define GAMEBOY_PAGE 0x26 //mapper byte specifies A15-8
#define GBA_ROM_PAGE 0x27 //address must have already been latched with gba dictionary
#define GENESIS_ROM_PAGE0 0x28 //bank address A17-23 must have been latched already
//TODO come up with better way to handle genesis address complications
#define GENESIS_ROM_PAGE1 0x29 //bank address A17-23 must have been latched already
#define N64_ROM_PAGE 0x30
//operand LSB
//SST 39SF0x0 manf/prod IDs

8
shared/shared_dict_n64.h
View File

@ -17,7 +17,11 @@
//=============================================================================================
#define N64_RD 0 //RL=3 return error code, data len = 1, 1 byte of data
#define N64_WR 1
#define N64_RD 0 //RL=4 return error code, data len = 1, 2 bytes of data (D0-15)
// TODO #define N64_WR 1
#define N64_SET_BANK 2 //operand = A16-31 for next address latch, this merely updates a firmware variable
#define N64_LATCH_ADDR 3 //operand = A0-15 (A0 ignored by rom), BANK from above used for A16-31
#define N64_RELEASE_BUS 4 //take ALE_L/H high to end the access
#endif

16
shared/shared_dict_pinport.h
View File

@ -163,6 +163,7 @@
#define ADDR_IP_ 15
#define ADDR_OP_ 16
#define ADDR_SET_ 17
#define ADDR_RD_ 26 //doesn't work on devices without direct access to 16bit address bus
//============================
//EXP PORT 8bit ACCESS (bits1-8)
@ -182,4 +183,19 @@
#define HADDR_DISABLE_ 22
#define HADDR_SET_ 23
// CTL_OD_ 24 above
// CTL_PP_ 25 above
// ADDR_RD_ 26 above
//============================
//FLIPFLOP ADDR PORT 8bit WIDE ACCESS
//SEGA: FF0-7 connecto to A17-18, #AS, A20-23, #TIME
//opcode: type of operation
//operand: value to place on bus
//NOTE: these operations corrupt the ADDR bus, so call this first
//============================
#define FFADDR_ENABLE_ 27
#define FFADDR_DISABLE_ 28
#define FFADDR_SET_ 29
#endif

5
shared/shared_dict_sega.h
View File

@ -16,8 +16,13 @@
//=============================================================================================
//=============================================================================================
//TODO THESE ARE JUST PLACE HOLDERS...
#define SEGA_RD 0 //RL=3 return error code, data len = 1, 1 byte of data
#define SEGA_WR 1
// GENESIS ADDR A17-23 along with #LO_MEM & #TIME
// TODO separate #LO_MEM & #TIME, they're currently fixed high
#define SET_BANK 2
#endif