modified: logic.h
modified: pinport.c modified: pinport.h -completing implementation of remaining shared_pinport opcodes modified: ../../shared/shared_pinport.h -few opcodes deleted because I decided they were stupid when got around to implementing them. Set user up for errors and not useful generally.
This commit is contained in:
Paul Molloy
parent
0af7bb3b16
commit
ce2a5aecca
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@ -6,10 +6,10 @@
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#define IP 0x00
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#define OP 0xFF
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//FALSE is ANYTHING but TRUE, the value signifies the error number
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#define TRUE 0x00
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#define SUCCESS 0x00
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#define ERR_UNKN_PP_OPCODE_ONLY 1
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#define ERR_UNKN_PP_OPCODE_8BOP 2
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#define ERR_UNKN_PP_OPCODE_16BOP 2
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#define ERR_UNKN_PP_OPCODE_ONLY 1
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#define ERR_UNKN_PP_OPCODE_8BOP 2
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#define ERR_UNKN_PP_OPCODE_16BOP 3
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#define ERR_UNKN_PP_OPCODE_24BOP 4
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#define ERR_UNKN_PP_OPCODE_8BRV 5
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@ -295,6 +295,7 @@ void software_AHL_CLK()
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* -FF latch /OE pins set as outputs
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* -FF CLK pins low ready for CLK
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* See big CAUTION on shared_pinport.h for more details
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* ADDR_OP() expected to be set
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* Post:Macro/function called with operand
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* data bus left free and clear when possible
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* -DATA_OPnSET diliberately drive the bus
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@ -309,11 +310,6 @@ uint8_t pinport_opcode_8b_operand( uint8_t opcode, uint8_t operand )
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case ADDR_SET:
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ADDR_OUT = operand;
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break;
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//convienent/safer sets OP then value
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case ADDR_OPnSET:
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_ADDR_OP();
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ADDR_OUT = operand;
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break;
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//DATA[7:0] PORTB
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case DATA_SET:
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@ -327,20 +323,14 @@ uint8_t pinport_opcode_8b_operand( uint8_t opcode, uint8_t operand )
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//ADDR[15:8] FLIPFLOP
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case ADDRH_SET:
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_DATA_OP();
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DATA_OUT = operand;
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_AHL_CLK();
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_DATA_IP();
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_ADDRH_SET(operand);
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break;
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//EXPANSION FLIPFLOP
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//NES: ADDRX[7:0] -> EXP PORT [8:1]
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//SNES: ADDRX[7:0] -> CPU A[23:16]
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case ADDRX_SET:
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_DATA_OP();
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DATA_OUT = operand;
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_AXL_CLK();
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_DATA_IP();
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_ADDRX_SET(operant);
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break;
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//Set ADDR/DATA bus DDR registers with bit granularity
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@ -381,8 +371,8 @@ uint8_t pinport_opcode_8b_operand( uint8_t opcode, uint8_t operand )
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/* Desc:Function takes an opcode and 16bit operand which was transmitted via USB
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* operand_MS is most significant byte, operand_LS is least significant
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* then decodes it to call designated macro/function.
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* operandMSB is most significant byte, operandLSB is least significant
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* shared_pinport.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_pinport.h
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@ -390,68 +380,61 @@ uint8_t pinport_opcode_8b_operand( uint8_t opcode, uint8_t operand )
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* control pins must be initialized
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* -FF latch /OE pins set as outputs
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* -FF CLK pins low ready for CLK
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* ADDR_OP() is expected to be set.
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* /ROMSEL and M2 expected to be OP.
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* See big CAUTION on shared_pinport.h for more details
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* Post:Macro/function called with operand
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* data bus left free and clear when possible
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* -some opcodes diliberately drive the bus
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* ADDR_OP() is left set as default state
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* Rtn: SUCCESS if opcode found, ERR_UNKN_PP_OPCODE_16BOP if opcode not present.
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*/
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uint8_t pinport_opcode_16b_operand( uint8_t opcode, uint8_t operand_MS, uint8_t operand_LS )
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uint8_t pinport_opcode_16b_operand( uint8_t opcode, uint8_t operandMSB, uint8_t operandLSB )
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{
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switch (opcode) {
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//ADDR[15:0] (ADDRH:ADDR)
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//Doesn't affect control signals
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//bits[13:0] are applied to NES CPU, NES PPU, and SNES address bus
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//bit[14] is only applied to CPU A14 on NES
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//bit[15] is only applied to PPU /A13 on NES
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//bit[15:14] are applied to SNES A[15:14]
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//ADDR[15:0] (ADDRH:ADDR)
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//Doesn't affect control signals
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//bits[13:0] are applied to NES CPU, NES PPU, and SNES address bus
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//bit[14] is only applied to CPU A14 on NES
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//bit[15] is only applied to PPU /A13 on NES
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//bit[15:14] are applied to SNES A[15:14]
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case ADDR16_SET:
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_DATA_OP();
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DATA_OUT =
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_ADDRH_SET(operandMSB);
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ADDR_OUT = operandLSB;
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break;
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//Set NES CPU ADDRESS BUS SET with /ROMSEL
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//bit 15 is decoded to enable /ROMSEL properly (aka PRG /CE)
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//bit15 is actually inverted then applied to /ROMSEL since /ROMSEL is low when NES CPU A15 is high
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//NOTE! This does NOT affect M2 (aka phi2), so carts using M2 to decode things like WRAM is dependent on last value of M2
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//This will also stop current value of PPU /A13 with bit15
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//Set NES CPU ADDRESS BUS SET with /ROMSEL
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//bit 15 is decoded to enable /ROMSEL properly (aka PRG /CE)
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//bit15 is actually inverted then applied to /ROMSEL since /ROMSEL is low when NES CPU A15 is high
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//NOTE! This does NOT affect M2 (aka phi2), so carts using M2 to decode things like WRAM is dependent on last value of M2
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//This will also stop current value of PPU /A13 with bit15
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case NCPU_ADDR_ROMSEL:
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_ADDRH_SET(operandMSB);
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ADDR_OUT = operandLSB;
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//if $8000 or higher
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if (operandMSB >= 0x80) _ROMSEL_LO();
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//else $7FFF or lower
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else _ROMSEL_HI();
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break;
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//Set NES CPU ADDRESS BUS SET with M2
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//Identical to NCPU_ADDR_ROMSEL above, but M2 (aka phi2) affected instead of /ROMSEL
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//bit 15 is decoded to assert M2 properly
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//bit15 is actually applied directly to M2 since carts use M2 being high as part of A15=1 detection
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//NOTE! This does NOT affect /ROMSEL, so /ROMSEL is whatever value it was previously
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//This will also stop current value of PPU /A13 with bit15
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case NCPU_ADDR_M2:
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break;
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//Set NES CPU ADDRESS BUS SET with M2 & /ROMSEL
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//Combination of opcodes above, but M2 and /ROMSEL will be asserted
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//bit 15 is decoded to assert M2 & /ROMSEL properly
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//bit15 is actually applied directly to M2 since carts use M2 being high as part of A15=1 detection
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//NOTE! This does NOT affect /ROMSEL, so /ROMSEL is whatever value it was previously
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//This will also stop current value of PPU /A13 with bit15
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case NCPU_ADDR_M2ROMSEL:
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break;
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//Set NES PPU ADDRESS BUS with /A13
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//PPU address bus is 14bits wide A[13:0] so operand bits [15:14] are ignored.
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//bit 13 is inverted and applied to PPU /A13
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//PPU control signals CHR /RD and CHR /WR are unaffected
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//Note: since PPU /A13 is tied to ADDRH[7] could perform this faster by using ADDR16_SET
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// but this opcode is convienent and ensures PPU /A13 is always inverse of PPU A13
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// This is important for NES carts with on board CHR-ROM and VRAM for 4screen mirroring.
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//Set NES PPU ADDRESS BUS with /A13
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//PPU address bus is 14bits wide A[13:0] so operand bits [15:14] are ignored.
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//bit 13 is inverted and applied to PPU /A13
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//PPU control signals CHR /RD and CHR /WR are unaffected
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//Note: since PPU /A13 is tied to ADDRH[7] could perform this faster by using ADDR16_SET
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// but this opcode is convienent and ensures PPU /A13 is always inverse of PPU A13
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// This is important for NES carts with on board CHR-ROM and VRAM for 4screen mirroring.
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case NPPU_ADDR_SET:
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ADDR_OUT = operandLSB;
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// below PPU $2000, A13 clear, SET PPU /A13
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if (operandMSB < 0x20) _ADDRH_SET(operandMSB & PPU_A13N);
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// above PPU $1FFF, A13 set, PPU /A13 already clear in operandMSB
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else _ADDRH_SET(operandMSB);
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break;
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default:
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//macro doesn't exist
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return ERR_UNKN_PP_OPCODE_16BOP;
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@ -460,11 +443,112 @@ uint8_t pinport_opcode_16b_operand( uint8_t opcode, uint8_t operand_MS, uint8_t
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return SUCCESS;
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}
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//=================================
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//24bit operand
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//=================================
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/* Desc:Function takes an opcode and 24bit operand which was transmitted via USB
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* then decodes it to call designated macro/function.
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* operandMSB is most signf byte, operandMID is center, operandLSB is least significant
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* shared_pinport.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_pinport.h
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* data bus must be free and clear
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* control pins must be initialized
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* -FF latch /OE pins set as outputs
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* -FF CLK pins low ready for CLK
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* ADDR_OP() is expected to be set.
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* See big CAUTION on shared_pinport.h for more details
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* Post:Macro/function called with operand
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* data bus left free and clear when possible
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* -some opcodes may diliberately drive the bus
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* ADDR_OP() is left set as default state
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* Rtn: SUCCESS if opcode found, ERR_UNKN_PP_OPCODE_24BOP if opcode not present.
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*/
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uint8_t pinport_opcode_24b_operand( uint8_t opcode, uint8_t operandMSB, uint8_t operandMID, uint8_t operandLSB )
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{
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//ADDR[23:0] (ADDRX:ADDRH:ADDR) SNES full address bus
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//Sets SNES 24 bit address but to value of 24bit operand
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//No control signals are modified
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//#define ADDR24_SET 0xB0
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switch (opcode) {
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//ADDR[23:0] (ADDRX:ADDRH:ADDR) SNES full address bus
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//Sets SNES 24 bit address but to value of 24bit operand
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//No control signals are modified
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case ADDR24_SET:
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ADDR_OUT = operandLSB;
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_DATA_OP();
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DATA_OUT = operandMID;
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_CLK_AHL();
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DATA_OUT = operandMSB;
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_CLK_AXL();
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DATA_IP();
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break;
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default:
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//macro doesn't exist
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return ERR_UNKN_PP_OPCODE_24BOP;
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}
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return SUCCESS;
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}
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/* Desc:Function takes an opcode and pointer to return value byte
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* then decodes it to retreive value.
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* shared_pinport.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_pinport.h
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* See big CAUTION on shared_pinport.h for more details
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* Post:pointer updated to value designated by opcode.
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* Rtn: SUCCESS if opcode found, ERR_UNKN_PP_OPCODE_8BRV if opcode not present.
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*/
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uint8_t pinport_opcode_8b_return( uint8_t opcode, uint8_t *rvalue )
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{
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switch (opcode) {
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//READ MCU I/O PORT INPUT 'PIN' REGISTERS
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//ADDR[7:0] PINA
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case ADDR_RD:
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rvalue = ADDR_IN;
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//DATA[7:0] PINB
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case DATA_RD:
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rvalue = DATA_IN;
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//CTL PINC
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case CTL_RD:
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rvalue = CTL_IN;
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//AUX PIND
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case AUX_RD:
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rvalue = AUX_IN;
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//READ MCU I/O PORT OUTPUT 'PORT' REGISTERS
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//ADDR[7:0] PORTA
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case ADDR_PORT_RD:
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rvalue = ADDR_OUT;
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//DATA[7:0] PORTB
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case DATA_PORT_RD:
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rvalue = DATA_OUT;
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//CTL PORTC
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case CTL_PORT_RD:
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rvalue = CTL_OUT;
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//AUX PORTD
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case AUX_PORT_RD:
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rvalue = AUX_OUT;
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//READ MCU I/O PORT DIRECTION 'DDR' REGISTERS
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//ADDR[7:0] DDRA
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case ADDR_DDR_RD:
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rvalue = ADDR_DDR;
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//DATA[7:0] DDRB
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case DATA_DDR_RD:
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rvalue = DATA_DDR:
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//CTL DDRC
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case CTL_DDR_RD:
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rvalue = CTL_DDR;
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//AUX DDRD
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case AUX_DDR_RD:
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rvalue = AUX_DDR;
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default:
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//macro doesn't exist
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return ERR_UNKN_PP_OPCODE_8BRV;
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}
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return SUCCESS;
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}
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@ -6,6 +6,8 @@
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uint8_t pinport_opcode_only( uint8_t opcode );
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uint8_t pinport_opcode_8b_operand( uint8_t opcode, uint8_t operand );
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uint8_t pinport_opcode_16b_operand( uint8_t opcode, uint8_t operandMSB, uint8_t operandLSB )
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uint8_t pinport_opcode_24b_operand( uint8_t opcode, uint8_t operandMSB, uint8_t operandMID, uint8_t operandLSB )
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void software_AHL_CLK();
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void software_AXL_CLK();
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@ -400,5 +402,14 @@ void software_AXL_CLK();
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#define _EXPFF_FLT() _XOE_hi();
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#endif
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//clocks must be initialized, Data bus clear
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#define _ADDRH_SET(oper) _DATA_OP(); DATA_OUT = oper; _AHL_CLK(); _DATA_IP();
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#define _ADDRX_SET(oper) _DATA_OP(); DATA_OUT = oper; _AXL_CLK(); _DATA_IP();
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//PPU A13 is ADDRH bit 5
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#define PPU_A13 0x20
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//PPU /A13 is ADDRH bit 7
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#define PPU_A13N 0x80
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#endif
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@ -217,6 +217,9 @@
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// ie driving PPU /A13 will be fed back to CIRAM /CE so it needs to be IP
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// -if in doubt, leave it as input with pull up, atleast that shouldn't break anything
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//
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// -ADDR_OP is default state, these opcodes assume it to be set as it shouldn't conflict
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// -/ROMSEL & M2 expected to be set as outputs
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//
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//
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//=============================================================================================
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//=============================================================================================
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@ -228,9 +231,9 @@
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// OPCODES WITH OPERAND and no return value besides SUCCESS/ERROR_CODE
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//=============================================================================================
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// 0x80-0x9F: opcodes with 8bit operand
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// 0x80-8B are only ones currently in use
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// 0x80-8A are only ones currently in use
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// 0xA0-0xAF: opcodes with 16bit operand
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// 0xA0-A4 are only ones currently in use
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// 0xA0-A2 are only ones currently in use
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// 0xB0-0xBF: opcodes with 24bit operand
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// 0xA0 is currently only one in use
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//
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@ -249,13 +252,11 @@
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//ADDR[7:0] PORTA
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#define ADDR_SET 0x80
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//conveinent/safe yet slower function that sets ADDR as OP then sets value
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#define ADDR_OPnSET 0x81
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//DATA[7:0] PORTB
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#define DATA_SET 0x82
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#define DATA_SET 0x81
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//conveinent/safe yet slower function that sets ADDR as OP then sets value
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#define DATA_OPnSET 0x83
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#define DATA_OPnSET 0x82
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//ADDR[15:8] FLIPFLOP
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//NES CPU: ADDRH[6:0] -> CPU A[14:8]
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@ -264,27 +265,27 @@
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// ADDRH[6] -> NC on PPU side
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// ADDRH[7] -> PPU /A13 (which drives CIRAM /CE on most carts "2-screen mirroring")
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//SNES: ADDRH[7:0] -> CPU A[15:8]
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#define ADDRH_SET 0x84
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#define ADDRH_SET 0x83
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//EXPANSION FLIPFLOP
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//NES: ADDRX[7:0] -> EXP PORT [8:1]
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//SNES: ADDRX[7:0] -> CPU A[23:16]
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#define ADDRX_SET 0x85
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#define ADDRX_SET 0x84
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//Set ADDR/DATA bus DDR registers with bit granularity
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// OP() IP() macros affect entire 8bit port's direction
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// Each pin can be controlled individually though
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// This could be useful for advanced feature that doesn't treat DATA/ADDR as byte wide port.
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#define ADDR_DDR_SET 0x86
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#define DATA_DDR_SET 0x87
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#define ADDR_DDR_SET 0x85
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#define DATA_DDR_SET 0x86
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//Perhaps it will be useful to have this function on other ports as well
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//But probably wouldn't be very useful if standard carts are plugged in..
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//AUX port operations will shield USB pins from being affected
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//defined as lower case because you shouldn't call these unless you *Really* know what you're doing..
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#define ctl_ddr_set 0x88
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#define aux_ddr_set 0x89
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#define ctl_port_set 0x8A
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#define aux_port_set 0x8B
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#define ctl_ddr_set 0x87
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#define aux_ddr_set 0x88
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#define ctl_port_set 0x89
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#define aux_port_set 0x8A
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//TODO consider listing AVR internal registers here..?
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//could be useful when utilizing SPI/I2C communications etc
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@ -310,22 +311,6 @@
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//This will also stop current value of PPU /A13 with bit15
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#define NCPU_ADDR_ROMSEL 0xA1
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//Set NES CPU ADDRESS BUS SET with M2
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//Identical to NCPU_ADDR_ROMSEL above, but M2 (aka phi2) affected instead of /ROMSEL
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||||
//bit 15 is decoded to assert M2 properly
|
||||
//bit15 is actually applied directly to M2 since carts use M2 being high as part of A15=1 detection
|
||||
//NOTE! This does NOT affect /ROMSEL, so /ROMSEL is whatever value it was previously
|
||||
//This will also stop current value of PPU /A13 with bit15
|
||||
#define NCPU_ADDR_M2 0xA2
|
||||
|
||||
//Set NES CPU ADDRESS BUS SET with M2 & /ROMSEL
|
||||
//Combination of opcodes above, but M2 and /ROMSEL will be asserted
|
||||
//bit 15 is decoded to assert M2 & /ROMSEL properly
|
||||
//bit15 is actually applied directly to M2 since carts use M2 being high as part of A15=1 detection
|
||||
//NOTE! This does NOT affect /ROMSEL, so /ROMSEL is whatever value it was previously
|
||||
//This will also stop current value of PPU /A13 with bit15
|
||||
#define NCPU_ADDR_M2ROMSEL 0xA3
|
||||
|
||||
//TODO consider opcode that preserves PPU /A13 instead of stomping it like the opcodes above.
|
||||
//Can't think of why this would be useful so ignoring for now
|
||||
//One reason might be to keep VRAM silent on a NES board with 4screen mirroring..
|
||||
|
|
@ -338,10 +323,8 @@
|
|||
//Note: since PPU /A13 is tied to ADDRH[7] could perform this faster by using ADDR16_SET
|
||||
// but this opcode is convienent and ensures PPU /A13 is always inverse of PPU A13
|
||||
// This is important for NES carts with on board CHR-ROM and VRAM for 4screen mirroring.
|
||||
#define NPPU_ADDR_SET 0xA4
|
||||
#define NPPU_ADDR_SET 0xA2
|
||||
|
||||
//TODO consider opcode that sets PPU A[12:0] and maintains previous value of A13 & /A13
|
||||
//might be useful if trying to latch/clock CHR memory with it's /CE pin instead of /OE /WE
|
||||
|
||||
//=================================
|
||||
//24bit operand
|
||||
|
|
@ -358,7 +341,7 @@
|
|||
// OPCODES with NO OPERAND but have RETURN VALUE plus SUCCESS/ERROR_CODE
|
||||
//=============================================================================================
|
||||
// 0xC0-0xFF: opcodes with 8bit return value (plus SuCCESS/ERROR)
|
||||
// 0xC0-CD are only ones currently in use
|
||||
// 0xC0-CB are only ones currently in use
|
||||
//
|
||||
// 0x??-0xFF: larger return values perhaps?
|
||||
//
|
||||
|
|
@ -375,45 +358,40 @@
|
|||
//Current value of PORT Determines if pullups are activated or not, pull up with HI() macro, and float with LO() macro
|
||||
//ADDR[7:0] PINA
|
||||
#define ADDR_RD 0xC0
|
||||
//conveinence fucntion sets as input then reads
|
||||
#define ADDR_INnRD 0xC1
|
||||
//DATA[7:0] PINB
|
||||
#define DATA_RD 0xC2
|
||||
//conveinence fucntion sets as input then reads
|
||||
#define DATA_INnRD 0xC3
|
||||
|
||||
#define DATA_RD 0xC1
|
||||
//CTL PINC
|
||||
//Should set pin of interest to input with IP with macros prior to reading
|
||||
//you're still allowed to read value even if some/all pins are output though
|
||||
#define CTL_RD 0xC4
|
||||
#define CTL_RD 0xC2
|
||||
//AUX PIND
|
||||
//Should set pin of interest to input with IP with macros prior to reading
|
||||
//you're still allowed to read value even if some/all pins are output though
|
||||
#define AUX_RD 0xC5
|
||||
#define AUX_RD 0xC3
|
||||
|
||||
|
||||
//READ MCU I/O PORT OUTPUT 'PORT' REGISTERS
|
||||
//Gives means to see what pins are currently being driven (or pulled up) to.
|
||||
//ADDR[7:0] PORTA
|
||||
#define ADDR_PORT_RD 0xC6
|
||||
#define ADDR_PORT_RD 0xC4
|
||||
//DATA[7:0] PORTB
|
||||
#define DATA_PORT_RD 0xC7
|
||||
#define DATA_PORT_RD 0xC5
|
||||
//CTL PORTC
|
||||
#define CTL_PORT_RD 0xC8
|
||||
#define CTL_PORT_RD 0xC6
|
||||
//AUX PORTD
|
||||
#define AUX_PORT_RD 0xC9
|
||||
#define AUX_PORT_RD 0xC7
|
||||
|
||||
|
||||
//READ MCU I/O PORT DIRECTION 'DDR' REGISTERS
|
||||
//Gives means to see what pins are currently set to I/P or O/P.
|
||||
//ADDR[7:0] DDRA
|
||||
#define ADDR_DDR_RD 0xCA
|
||||
#define ADDR_DDR_RD 0xC8
|
||||
//DATA[7:0] DDRB
|
||||
#define DATA_DDR_RD 0xCB
|
||||
#define DATA_DDR_RD 0xC9
|
||||
//CTL DDRC
|
||||
#define CTL_DDR_RD 0xCC
|
||||
#define CTL_DDR_RD 0xCA
|
||||
//AUX DDRD
|
||||
#define AUX_DDR_RD 0xCD
|
||||
#define AUX_DDR_RD 0xCB
|
||||
|
||||
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue