139 lines
3.1 KiB
C
139 lines
3.1 KiB
C
#ifndef _shared_enums_h
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#define _shared_enums_h
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//One concise place to list all enums used
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//for setting cartridge and memory elements on the host
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//which end up getting communicated between device and host
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//used to denote when any cartridge element is not known
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#define UNKNOWN 0xFF
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//console options
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#define NES_CART 'N'
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#define FC_CART 'F'
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#define SNES_CART 'S'
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#define BKWD_CART 'B'
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//NES mappers
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#define NROM 0
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#define MMC1 1
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#define CNROM 2
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#define UxROM 3
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#define MMC3 4
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#define MMC5 5
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#define AxROM 7
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#define MMC2 9
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#define MMC4 10
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#define CDREAMS 11
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#define A53 28
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#define UNROM512 30
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#define EZNSF 31
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#define BxROM 34
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#define RAMBO 64
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#define H3001 65 //IREM mapper
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#define GxROM 66
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#define SUN3 67
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#define SUN4 68
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#define FME7 69 //SUNSOFT-5 with synth
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#define HDIVER 78
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#define DxROM 205
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// UNKNOWN 255 don't assign to something meaningful
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enum mirroring {
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MIR_1SCNA = 0x10, //SCNA
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MIR_1SCNB = 0x11, //SCNB
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MIR_VERT = 0x12, //VERT
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MIR_HORIZ = 0x13, //HORIZ
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MIR_ANROM,
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MIR_MMC1,
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MIR_MMC3,
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MIR_FME7
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};
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enum operations {
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READ = 10,
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WRITE,
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CHECK
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};
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//SST 39SF0x0 manf/prod IDs
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#define SST_MANF_ID 0xBF
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#define SST_PROD_128 0xB5
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#define SST_PROD_256 0xB6
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#define SST_PROD_512 0xB7
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//SRAM manf/prod ID
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#define SRAM 0xAA
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//MASK ROM read only
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#define MASKROM 0xDD
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enum buff_mem_type {
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PRGROM = 10,
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CHRROM,
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PRGRAM,
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SNESROM,
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SNESRAM
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};
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//buffer/operation status values
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#define EMPTY 0x00
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#define RESET 0x01
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#define PROBLEM 0x10
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#define PREPARING 0x20
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#define USB_UNLOADING 0x80
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#define USB_LOADING 0x90
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#define USB_FULL 0x98
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#define CHECKING 0xC0
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#define DUMPING 0xD0
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#define STARTDUMP 0xD2
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#define DUMPED 0xD8
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#define ERASING 0xE0
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#define FLASHING 0xF0
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#define STARTFLASH 0xF2
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#define FLASHED 0xF4
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#define FLASH_WAIT 0xF8
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#define STOPPED 0xFE
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#define UNALLOC 0xFF
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enum addr_high_direct_mask {
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//actual value is part mapper dependent and part flash dependent
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//mapper controlled address bits dictate where split is
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//32KB banking A14-0 NES ctl, A15+ mapper ctl "bank" NROM, BNROM, ANROM
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//addrH_dmask = 0b0111 1111 directly addressable addrH bits
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MSK_32KB = 0x7F,
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//16KB banking A13-0 NES ctl, A14+ mapper ctl "bank" UxROM, MMC1
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//addrH_dmask = 0b0011 1111
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MSK_16KB = 0x3F,
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// 8KB banking A12-0 NES ctl, A13+ mapper ctl "bank" MMC3, FME7, CHR discrete banking
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//addrH_dmask = 0b0001 1111
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MSK_8KB = 0x1F,
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// 4KB banking A11-0 NES ctl, A12+ mapper ctl "bank" ezNSF MMC1 CHR
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//addrH_dmask = 0b0000 1111
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MSK_4KB = 0x0F,
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// 2KB banking A10-0 NES ctl, A11+ mapper ctl "bank" MMC3 CHR
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//addrH_dmask = 0b0000 0111
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MSK_2KB = 0x07,
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// 1KB banking A9-0 NES ctl, A10+ mapper ctl "bank" FME7 CHR
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//addrH_dmask = 0b0000 0011
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MSK_1KB = 0x03
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};
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enum page2bankshiftright {
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//A15->A8 = 7 shifts (equal to number of set bits in addrH_mask
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PG2B_32KB = 7,
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//A14->A8 = 6 shifts
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PG2B_16KB = 6,
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//A13->A8 = 5 shifts
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PG2B_8KB = 5,
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//A12->A8 = 4 shifts
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PG2B_4KB = 4,
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//A11->A8 = 3 shifts
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PG2B_2KB = 3,
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//A10->A8 = 2 shifts
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PG2B_1KB = 2
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};
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#endif
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