118 lines
4.5 KiB
C
118 lines
4.5 KiB
C
#ifndef _shared_dict_nes_h
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#define _shared_dict_nes_h
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//define dictionary's reference number in the shared_dictionaries.h file
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//then include this dictionary file in shared_dictionaries.h
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//The dictionary number is literally used as usb transfer request field
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//the opcodes and operands in this dictionary are fed directly into usb setup packet's wValue wIndex fields
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//=============================================================================================
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//=============================================================================================
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// NES DICTIONARY
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//
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// opcodes contained in this dictionary must be implemented in firmware/source/nes.c
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//
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//=============================================================================================
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//=============================================================================================
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// OPCODES with no operand and no return value besides SUCCESS/ERROR_CODE
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//Discrete board PRG-ROM only write, does not write to mapper
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//This is a /WE controlled write with data latched on rising edge EXP0
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//PRG-ROM /WE <- EXP0 w/PU
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//PRG-ROM /OE <- /ROMSEL
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//PRG-ROM /CE <- GND
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//PRG-ROM write: /WE & /CE low, /OE high
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//mapper '161 CLK <- /ROMSEL
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//mapper '161 /LOAD <- PRG R/W
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//wValueMSB: data
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//wIndex: address
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#define DISCRETE_EXP0_PRGROM_WR 0x00
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#define NES_PPU_WR 0x01
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//generic CPU write with M2 toggle as expected with NES CPU
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// A15 decoded to enable /ROMSEL as it should
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#define NES_CPU_WR 0x02
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//#define DISCRETE_EXP0_MAPPER_WR 0x03
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//write to an MMC1 register, provide bank/address & data
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#define NES_MMC1_WR 0x04
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#define NES_DUALPORT_WR 0x05
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#define DISC_PUSH_EXP0_PRGROM_WR 0x06
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#define MMC3_PRG_FLASH_WR 0x07 //TODO set return lengths for all these functions
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#define MMC3_CHR_FLASH_WR 0x08
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#define NROM_PRG_FLASH_WR 0x09
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#define NROM_CHR_FLASH_WR 0x0A
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#define CNROM_CHR_FLASH_WR 0x0B //needs cur_bank & bank_table prior to calling
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#define CDREAM_CHR_FLASH_WR 0x0C //needs cur_bank & bank_table prior to calling
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#define UNROM_PRG_FLASH_WR 0x0D //needs cur_bank & bank_table prior to calling
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#define MMC1_PRG_FLASH_WR 0x0E
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#define MMC1_CHR_FLASH_WR 0x0F //needs cur_bank set prior to calling
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#define MMC4_PRG_SOP_FLASH_WR 0x10 //current bank must be selected, & needs cur_bank set prior to calling
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#define MMC4_CHR_FLASH_WR 0x11 //needs cur_bank set prior to calling
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#define MAP30_PRG_FLASH_WR 0x12 //needs cur_bank set prior to calling
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#define GTROM_PRG_FLASH_WR 0x13 //desired bank must be selected
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#define MMC4_PRG_FLASH_WR 0x14 //mapper mod to XOR A14 with A13
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#define SET_CUR_BANK 0x20
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#define SET_BANK_TABLE 0x21
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#define M2_LOW_WR 0x22 //like CPU WR, but M2 stays low
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//write a page worth of random data to ppu
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//make sure the LSFR is initialized first in misc dict
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//send start address in operand, doesn't have to be page boundary
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//but A13 and /A13 get set once based on provided address.
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#define PPU_PAGE_WR_LFSR 0x23
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#define SET_NUM_PRG_BANKS 0x24 //used for determining banktable structure for mapper 11 and such
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#define M2_HIGH_WR 0x25 //like CPU WR, but M2 stays high
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#define FLASH_3V_WR 0x25 //same as above but easier to remember when
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//being used to write to 3v tssop flash
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#define MMC3S_PRG_FLASH_WR 0x26 //TODO set return lengths for all these functions
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//=============================================================================================
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// OPCODES WITH OPERAND AND RETURN VALUE plus SUCCESS/ERROR_CODE
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//=============================================================================================
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//read from NES CPU ADDRESS
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//set /ROMSEL, M2, and PRG R/W
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//read from cartridge just as NES's CPU would
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//nice and slow trying to be more like the NES
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#define EMULATE_NES_CPU_RD 0x80 //RL=3
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//like the one above but not so slow..
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#define NES_CPU_RD 0x81 //RL=3
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#define NES_PPU_RD 0x82 //RL=3
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//doesn't have operands just returns sensed CIRAM A10 mirroring
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//now used to detect old firmware versions so NESmaker folks don't have to update firmware
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#define CIRAM_A10_MIRROR 0x83 //RL=3
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////returns VERT/HORIZ/1SCNA/1SCNB values:
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// #define MIR_1SCNA 0x10
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// #define MIR_1SCNB 0x11
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// #define MIR_VERT 0x12
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// #define MIR_HORZ 0x13
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#define NES_DUALPORT_RD 0x84 //RL=3
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#define GET_CUR_BANK 0x85 //RL=3
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#define GET_BANK_TABLE 0x86 //RL=4 16bit value so 2 bytes need returned
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#define GET_NUM_PRG_BANKS 0x87 //RL=3
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#define MMC5_PRG_RAM_WR 0x88 //RL=3 Enable writting to PRG-RAM and then write a single byte
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//after written read back for verification as a timeout would cause fail
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#endif
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