307 lines
9.6 KiB
C
307 lines
9.6 KiB
C
#include "flash.h"
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uint8_t write_page( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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// extern operation_info *oper_info;
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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//need to make address and unlock data variable
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//best for host to communcate these values
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//actual value is part mapper dependent and part flash dependent
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//mapper controlled address bits dictate where split is
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//32KB banking A14-0 NES ctl, A15+ mapper ctl "bank" NROM, BNROM, ANROM
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//addrH_dmask = 0b0111 1111 directly addressable addrH bits
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//page2bankshft = A14->A8 = 7 shifts (equal to number of set bits in addrH_mask
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//16KB banking A13-0 NES ctl, A14+ mapper ctl "bank" UxROM, MMC1
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//addrH_dmask = 0b0011 1111
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//page2bankshft = A13->A8 = 6 shifts
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// 8KB banking A12-0 NES ctl, A13+ mapper ctl "bank" MMC3, FME7
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//addrH_dmask = 0b0001 1111
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//page2bankshft = A12->A8 = 5 shifts
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// 4KB banking A11-0 NES ctl, A12+ mapper ctl "bank" ezNSF
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//addrH_dmask = 0b0000 1111
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//page2bankshft = A11->A8 = 4 shifts
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wr_func( 0x5555, 0xAA );
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// wr_func( oper_info->unlock1_AH, oper_info->unlock1_AL, oper_info->unlock1_data );
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wr_func( 0x2AAA, 0x55 );
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// wr_func( oper_info->unlock2_AH, oper_info->unlock2_AL, oper_info->unlock2_data );
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wr_func( 0x5555, 0xA0 );
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// wr_func( oper_info->command_AH, oper_info->command_AL, oper_info->command1_data );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//TODO verify byte is value that was trying to be flashed
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//move on to next byte
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n++;
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cur++;
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_chr( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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// extern operation_info *oper_info;
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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//need to make address and unlock data variable
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//best for host to communcate these values
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//actual value is part mapper dependent and part flash dependent
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//mapper controlled address bits dictate where split is
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//32KB banking A14-0 NES ctl, A15+ mapper ctl "bank" NROM, BNROM, ANROM
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//addrH_dmask = 0b0111 1111 directly addressable addrH bits
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//page2bankshft = A14->A8 = 7 shifts (equal to number of set bits in addrH_mask
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//16KB banking A13-0 NES ctl, A14+ mapper ctl "bank" UxROM, MMC1
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//addrH_dmask = 0b0011 1111
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//page2bankshft = A13->A8 = 6 shifts
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// 8KB banking A12-0 NES ctl, A13+ mapper ctl "bank" MMC3, FME7
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//addrH_dmask = 0b0001 1111
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//page2bankshft = A12->A8 = 5 shifts
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// 4KB banking A11-0 NES ctl, A12+ mapper ctl "bank" ezNSF
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//addrH_dmask = 0b0000 1111
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//page2bankshft = A11->A8 = 4 shifts
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wr_func( 0x1555, 0xAA );
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// wr_func( oper_info->unlock1_AH, oper_info->unlock1_AL, oper_info->unlock1_data );
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wr_func( 0x0AAA, 0x55 );
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// wr_func( oper_info->unlock2_AH, oper_info->unlock2_AL, oper_info->unlock2_data );
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wr_func( 0x1555, 0xA0 );
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// wr_func( oper_info->command_AH, oper_info->command_AL, oper_info->command1_data );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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//wr_func( ((addrH<<8)| n), buff->page_num );
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//wr_func( ((addrH<<8)| n), addrH);
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//TODO verify byte is value that was trying to be flashed
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//move on to next byte
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n++;
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cur++;
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_snes( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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// extern operation_info *oper_info;
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// uint8_t cur_data = buff->data[n];
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#ifdef AVR_CORE
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wdt_reset();
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#endif
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//set to program mode for first entry
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EXP0_LO();
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//enter unlock bypass mode
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wr_func( 0x0AAA, 0xAA );
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wr_func( 0x0555, 0x55 );
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wr_func( 0x0AAA, 0x20 );
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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//need to make address and unlock data variable
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//best for host to communcate these values
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//actual value is part mapper dependent and part flash dependent
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//mapper controlled address bits dictate where split is
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//32KB banking A14-0 NES ctl, A15+ mapper ctl "bank" NROM, BNROM, ANROM
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//addrH_dmask = 0b0111 1111 directly addressable addrH bits
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//page2bankshft = A14->A8 = 7 shifts (equal to number of set bits in addrH_mask
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//16KB banking A13-0 NES ctl, A14+ mapper ctl "bank" UxROM, MMC1
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//addrH_dmask = 0b0011 1111
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//page2bankshft = A13->A8 = 6 shifts
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// 8KB banking A12-0 NES ctl, A13+ mapper ctl "bank" MMC3, FME7
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//addrH_dmask = 0b0001 1111
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//page2bankshft = A12->A8 = 5 shifts
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// 4KB banking A11-0 NES ctl, A12+ mapper ctl "bank" ezNSF
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//addrH_dmask = 0b0000 1111
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//page2bankshft = A11->A8 = 4 shifts
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//
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//unlocked wr_func( 0x0AAA, 0xAA );
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//unlocked wr_func( 0x0555, 0x55 );
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//wr_func( 0x0000, 0xA0 );
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snes_rom_wr_cur_addr( 0xA0 ); //gained ~3KBps (59.13KBps) inl6 with v3.0 proto
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wr_func( ((addrH<<8)| n), buff->data[n] );
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//wr_func( ((addrH<<8)| n), cur_data ); //didn't actually speed up
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//Targetting 2MByte 16mbit flash which doesn't have buffered writes
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//currently have average flash speed of 21.05KBps going to start removing some of these NOPs
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//and optimizing flash routine to get time down.
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//exit program mode
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EXP0_HI();
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//pre-fetch next byte of data
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//cur_data = buff->data[n+1];
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#ifdef AVR_CORE
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wdt_reset();
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#endif
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//wait for byte to flash
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// do {
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// usbPoll();
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// read = rd_func((addrH<<8)|n);
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//
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// //} while( read != rd_func((addrH<<8)|n) );
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// } while( read != buff->data[n] );
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//this can cause things to hang on failed programs..
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//need a smarter flash polling algo, kind of a pain because we don't have
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//a good way to toggle /OE or /CE quickly on v3 SNES boards
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usbPoll();
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read = rd_func((addrH<<8)|n);
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//prepare for upcoming write cycle, or allow for a polling read
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EXP0_LO();
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//First check if already outputting final data
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if (read != buff->data[n] ) {
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//if not, lets see if toggle is occuring
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EXP0_HI();
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while( read != rd_func((addrH<<8)|n) ){
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EXP0_LO();
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NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP();
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EXP0_HI();
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read = rd_func((addrH<<8)|n);
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}
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//prepare for upcoming write cycle
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EXP0_LO();
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}
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// //IDK why, but AVR will exit early sometimes
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// //without this second check, ~20 errors per 32KByte on SNES v3.0
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// //All error bytes are 0xFF instead of true data
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// //may need a smarter flash polling routine..
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// //Tried to add extra delay to read algo, and didn't change anything
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// //Also have decent trust in read routine as it's comparable to page read
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// //which works flawlessly for dumps. So think it has to do with flashing specifically...
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// //Hmm maybe the avr is missing a read.. flash /CE, /OE, and /WE never toggle
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// //so why would flash polling output different data between polls..?
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// //Ahh this is the issue, adding the code below only adds delay which gives flash
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// //enough time to complete write.
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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//exit unlock bypass mode
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wr_func( 0x0000, 0x90 );
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wr_func( 0x0000, 0x00 );
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//reset the flash chip, supposed to exit too
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wr_func( 0x0000, 0xF0 );
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//exit program mode
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EXP0_HI();
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return SUCCESS;
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}
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/* Desc:Flash buffer contents on to cartridge memory
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* Pre: buffer elements must be updated to designate how/where to flash
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* buffer's cur_byte must be cleared or set to where to start flashing
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* mapper registers must be initialized
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* Post:buffer page flashed/programmed to memory.
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* Rtn: SUCCESS or ERROR# depending on if there were errors.
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*/
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uint8_t flash_buff( buffer *buff ) {
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uint8_t addrH = buff->page_num; //A15:8 while accessing page
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//First need to initialize mapper register bits
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//Perhaps this only needs to be done on first buffer though..?
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//Actually think this is best handled from buffer.c in operation == STARTFLASH
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//TODO use mapper to set mapper controlled address bits
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//need to calculate current bank and addrH
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//TODO set unlock addresses based on what works for that mapper and how it's banks are initialized
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//use mem_type to set addrH/X as needed for dump loop
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//also use to get read function pointer
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switch ( buff->mem_type ) {
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case PRGROM: //$8000
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write_page( 0, (0x80 | addrH), buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
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break;
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case CHRROM: //$0000
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write_page_chr( 0, addrH, buff, nes_ppu_wr, nes_ppu_rd );
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break;
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case PRGRAM:
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//addrH |= 0x60; //$6000
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//buff->cur_byte = nes_cpu_page_wr_poll( buff->data, addrH, buff->id,
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// buff->last_idx, ~FALSE );
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break;
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case SNESROM:
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addrH |= 0x80; //$8000 LOROM space
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//need to split page_num
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//A14-8 page_num[7-0]
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//A15 high (LOROM)
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//A23-16 page_num[14-8]
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HADDR_SET( (buff->page_num)>>7 );
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write_page_snes( 0, addrH, buff, snes_rom_wr, snes_rom_rd );
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case SNESRAM:
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//warn addrX = ((buff->page_num)>>8);
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break;
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default:
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return ERR_BUFF_UNSUP_MEM_TYPE;
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}
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//lets start just reading first page of PRG-ROM then get fancy
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// while (buff->cur_byte < buff->last_idx) {
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//
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// //might be faster to put some of these in new pointers, but not sure..
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// buff->data[buff->cur_byte] = nes_cpu_rd( addrH, buff->cur_byte );
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// buff->cur_byte++;
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// }
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return SUCCESS;
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}
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