396 lines
11 KiB
C
396 lines
11 KiB
C
#include "swim.h"
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//=================================================================================================
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//
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// SWIM operations
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// This file includes all the swim functions possible to be called from the swim dictionary.
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//
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// See description of the commands contained here in shared/shared_dictionaries.h
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//
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//=================================================================================================
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/* Desc:Function takes an opcode which was transmitted via USB
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* then decodes it to call designated function.
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* shared_dict_swim.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_dict_swim.h
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* Post:function call complete.
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* Rtn: SUCCESS if opcode found, error if opcode not present or other problem.
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*/
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uint8_t swim_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata )
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{
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#define RD_LEN 0
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#define RD0 1
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#define RD1 2
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#define BYTE_LEN 1
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#define HWORD_LEN 2
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switch (opcode) {
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case SWIM_ACTIVATE: swim_activate(); break;
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case SWIM_RESET: swim_reset(); break;
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case SWIM_SRST:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = swim_out( 0x0000, 4); break;
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case WOTF:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = swim_woft(operand, miscdata); break;
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// case ROTF:
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// rdata[RD_LEN] = BYTE_LEN;
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// rdata[RD0] = swim_roft(); break;
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default:
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//opcode doesn't exist
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return ERR_UNKN_SWIM_OPCODE;
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}
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return SUCCESS;
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}
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uint8_t swim_pin;
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uint16_t swim_mask;
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GPIO_TypeDef *swim_base;
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void delay( uint16_t delay )
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{
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uint16_t i = 0;
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for( i=0; i<delay; i++) {
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NOP();
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NOP();
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} //16->11.8 on stmad
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}
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/* Desc:Initiate SWIM activate sequence
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* Pre: swim_pin must be set and initialized via io.h
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* Post:STM8 mcu SWIM active
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* Rtn: SUCCESS if able to enter sucessfully.
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*/
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void swim_activate()
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{
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uint16_t i;
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// pinport_call( CTL_OP_, 0, swim_pin, 0);
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//toggles in this manner take 4.55-4.6usec on AVR
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//toggles in this manner take 4.9-4.95usec on STM adapter
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//pulse low for 16usec spec says 16usec
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//but looking at working programmers they do twice the delays below
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pinport_call( CTL_SET_LO_, 0, swim_pin, 0);
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delay(16);
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pinport_call( CTL_SET_HI_, 0, swim_pin, 0);
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//toggle high->low T=1msec 4x
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for( i = 0; i < 4; i++) {
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//STM adapter 720 = 500.9usec
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//TODO move this timed code into a timer to make timing more stable
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//between boards, pinport.c code, etc....
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#ifdef STM_INL6
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delay(719);
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#endif
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#ifdef STM_ADAPTER
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delay(720);
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#endif
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pinport_call( CTL_SET_LO_, 0, swim_pin, 0);
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delay(718);
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pinport_call( CTL_SET_HI_, 0, swim_pin, 0);
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}
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//toggle high->low T=0.5msec 4x
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for( i = 0; i < 4; i++) {
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//STM adapter 358 = 256usec
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delay(356);
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pinport_call( CTL_SET_LO_, 0, swim_pin, 0);
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delay(355);
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pinport_call( CTL_SET_HI_, 0, swim_pin, 0);
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}
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//pinport_call( CTL_IP_PU_, 0, swim_pin, 0);
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//wait for device to take swim_pin low for ~16usec
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//it's low for 128 SWIM clock sync pulse
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//Best way to do this would be to wait for an interrupt
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//on the swim pin going low, then have the isr count
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//low time. If anything takes too long timeout.
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//TODO
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//return SUCCESS/FAIL depending on wether that ~16usec pulse was obtained
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// return SUCCESS;
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}
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/* Desc:Hold swim pin low for >128 SWIM clocks (16usec)
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* Pre: swim must be activated by
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* Post:STM8 mcu SWIM comms are reset
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* Rtn: SUCCESS if device responds with sync window.
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*/
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void swim_reset()
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{
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//pinport_call( CTL_OP_, 0, swim_pin, 0);
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//pulse low for 16usec spec says 16usec
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//but looking at working programmers they do very long resets
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pinport_call( CTL_SET_LO_, 0, swim_pin, 0);
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delay(16);
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pinport_call( CTL_SET_HI_, 0, swim_pin, 0);
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}
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#define mov_swim_mask_r0() __asm ("mov r0, %[val]" : : [val] "r" (swim_mask) : "r0" )
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#define mov_pushpull_r6() __asm ("mov r6, %[val]" : : [val] "r" (pushpull) : "r6" )
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#define mov_opendrain_r7() __asm ("mov r7, %[val]" : : [val] "r" (opendrain) : "r7" )
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//BSRR 0x18
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#define str_r0_bset() __asm volatile ("strh r0, [%[mmio], #0x18]" : : [mmio] "r" (swim_base))
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//BRR 0x28
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#define str_r0_bres() __asm volatile ("strh r0, [%[mmio], #0x28]" : : [mmio] "r" (swim_base))
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//OTYPER 0x04
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#define pp_swim() __asm volatile ("strh r6, [%[mmio], #0x04]" : : [mmio] "r" (swim_base))
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#define od_swim() __asm volatile ("strh r7, [%[mmio], #0x04]" : : [mmio] "r" (swim_base))
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#define NO_RESP 0xFF
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#define ACK 0x01
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#define NAK 0x00
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/* Desc:Transfer SWIM bit stream
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* Always outputs '0' as first bit for header "from host"
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* Will output len number of bits plus one for header
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* Pre: swim_pin must be set and initialized via io.h
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* stream has first data bit stored in bit15 - bit[15-len+2]
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* pairity bit must be last bit in stream sequence bit[15-len+1]
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* ie bit7 contains pairity bit for 8bit data stream
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* Post:STM8 mcu SWIM active
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* Rtn: 0xFF if no response, 0-NAK, 1-ACK.
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*/
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uint8_t swim_out(uint16_t stream, uint8_t len)//, GPIO_TypeDef *base)
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{
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//__asm("swim_out_begin:\n\t");
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uint8_t return_val;
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uint16_t pushpull = swim_base->OTYPER & ~swim_mask;
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uint16_t opendrain = swim_base->OTYPER | swim_mask;
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mov_swim_mask_r0(); //will store r0 to BSRR or BRR to set/clear
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mov_pushpull_r6(); //will store r7 to OTYPER to drive high
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mov_opendrain_r7(); //will store r6 to OTYPER to allow device to drive low
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//store len in r5
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__asm volatile ("mov r5, %[val]" : : [val] "r" (len) : "r5" );
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//set flags so first bit is header '0' "from host"
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//the stream comes in as 16bit value with stream bit 7 in bit position 15
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//shift the stream left so the current transfer bit is in bit position 31
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//15 -> 30 is 15bit shifts, this leaves header zero in bit position 31
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//store stream in r4
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__asm volatile ("mov r4, %[val]" : : [val] "r" (stream) : "r4" );
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__asm volatile ("lsl r4, #15" : : : "r4", "cc" );
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//NOTE! cortex M0 only supports 'S' versions of lsl, sub, and, etc type
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//opcodes. I get compiler error for including the 's' at end of instruction
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//but lsl is same as lsls on M0, so just use lsl to avoid compiler error...
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// bit start:
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__asm("bit_start:\n\t");
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//always start going low
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str_r0_bres();
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//current bit is stored in bit31 and Negative flag is set if
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//current bit is '1'
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__asm volatile ("bpl cur_bit_zero\n\t");
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//go high since current bit is '1'
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pp_swim();
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str_r0_bset();
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od_swim();
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__asm volatile ("b det_next_bit\n\t");
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__asm("cur_bit_zero:\n\t");
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//must delay same amount of time as instructions above since branch
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//add delay here until '1' and '0' are same length
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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NOP();
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__asm("det_next_bit:\n\t");
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//determine if this is the last bit
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__asm volatile ("sub r5, #0x01" : : : "r5", "cc" );
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//if last bit, go to stream end to prepare for ACK/NAK latch
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__asm volatile ("bmi stream_end\n\t");
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//determine next bit value
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__asm volatile ("lsl r4, #1" : : : "r4", "cc" );
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//Negative flag is now set for '1', and clear for '0'
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//delay until 'go high' time for '0'
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//add delay here to make all bit transfers longer
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP();
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//always go high for '0' (no effect if already high for '1')
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pp_swim();
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str_r0_bset();
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od_swim();
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//go to bit start
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__asm volatile ("b bit_start\n\t");
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//stream end:
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__asm("stream_end:\n\t");
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//delay until 'go high' time for '0'
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP();
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//always go high for '0' (no effect if already high for '1')
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pp_swim();
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str_r0_bset();
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od_swim();
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//delay until time to latch ACK/NAK from device
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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//8x NOP's misread at times...
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//6x NOP's always misread, so must be too early
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NOP(); //9x NOP's and we're getting stable reads
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//first need to ensure device is actually responding
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//sample when output should be low for a 1 or 0
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//str_r0_bres(); //debug set low to denote when swim pin is being sampled with logic anaylzer
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//sampling ~100nsec into bit transfer (low for 125nsec min)
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//latch SWIM pin value from IDR 0x10
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__asm volatile ("ldrh r3, [%[mmio], #0x10]" : : [mmio] "r" (swim_base) : "r3");
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__asm volatile ("and r3, r0" : : : "r3", "cc" );
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//if it wasn't low, then the device didn't respond, so return error designating that
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//__asm volatile ("bne no_response\n\t");
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__asm ("mov %[rv], r3" : [rv] "=r" (return_val) );
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if (return_val != 0) {
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return NO_RESP;
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}
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//now delay until ~half way through bit transfer to sense 1-ACK or 0-NAK
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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//sampling 1.35usec into bit transfer (~half way)
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NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP(); NOP();
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//sampling 2.00usec into bit transfer oscope shows 2.7volts on stmad w/open drain
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//debug set low to denote when swim pin is being sampled with logic anaylzer
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//str_r0_bres();
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//pp_swim();
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//latch SWIM pin value from IDR 0x10
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__asm volatile ("ldr r3, [%[mmio], #0x10]" : : [mmio] "r" (swim_base) : "r3");
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__asm volatile ("and r3, r0" : : : "r3", "cc" );
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//move r3 to return val reg
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__asm volatile ("mov %[rv], r3" : [rv] "=r" (return_val) );
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//mask out swim pin so return value is 0 or non-zero based on device output
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//return_val &= swim_mask;
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if (return_val == 0x00) {
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return NAK;
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}
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//made it to here then we got an ACK
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return ACK;
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}
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/* Function to get parity of number n. It returns 0
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* if n has odd parity, and returns 0xFF if n has even
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* parity */
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uint16_t append_pairity(uint8_t n)
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{
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//shift incoming data to upper byte
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uint16_t data_pb = (n<<8);
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uint8_t parity = 0;
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while (n) {
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parity = ~parity;
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n = n & (n - 1);
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}
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if ( parity ) {
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return (data_pb | 0x80);
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} else {
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return data_pb;
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}
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}
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/* Desc:write byte to SWIM
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* Pre: swim must be activated
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* Post:
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* Rtn: 0-NAK, 1-ACK beware, no response looks like ACK!
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*/
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uint8_t swim_woft(uint16_t addr, uint8_t data)
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{
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uint16_t data_pb;
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uint8_t ack;
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uint8_t len = 0;
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//bit sequence:
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//1bit header "0" Host comm
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//3bit command b2-1-0 "010" WOTF
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//1bit pairity xor of cmd "1"
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//1bit ACK "1" or NAK "0" from device
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// 0b0_0101
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data_pb = 0x5000;
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// data_pb = 0x4000; //test wrong pairity
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len = 4; //data + pairity ( '0' header not included)
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ack = swim_out( data_pb, len);
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if (ack == NO_RESP) {
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return NO_RESP;
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} else if (ack == NAK) {
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return NAK;
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//wait and resend WOFT command
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}
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//write N "number of bytes for WOTF"
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data_pb = 0x0180;
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len = 9;
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ack = swim_out( data_pb, len);
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if (ack == NO_RESP) return NO_RESP;
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//write @E extended address of write
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//always 0x00 since targetting stm8s003 which only has one section
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data_pb = 0x0000;
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len = 9;
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ack = swim_out( data_pb, len);
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if (ack == NO_RESP) return NO_RESP;
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//write @H high address of write
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data_pb = append_pairity( addr>>8 );
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len = 9;
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ack = swim_out( data_pb, len);
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if (ack == NO_RESP) return NO_RESP;
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//write @L high address of write
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data_pb = append_pairity( addr );
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len = 9;
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ack = swim_out( data_pb, len);
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if (ack == NO_RESP) return NO_RESP;
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//write DATA portion of write
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data_pb = append_pairity( data );
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len = 9;
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ack = swim_out( data_pb, len);
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//More bytes can be written
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//any time NAK is recieved must resend byte
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return ack;
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}
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