1126 lines
36 KiB
C
1126 lines
36 KiB
C
#ifndef _pinport_al_h
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#define _pinport_al_h
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//Define the board type in makefile
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//#define AVR_KAZZO
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//#define STM_ADAPTER
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//#define STM_INL6
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#ifdef AVR_CORE
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#include "avr_gpio.h"
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#include <avr/wdt.h>
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#elif STM_CORE
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#include <stm32f0xx.h>
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#endif
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//This file contains pinout translations from AVR names to "kazzo" names
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//this file also works to make all kazzo versions compatible and "alike"
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//There are defines for kazzo version, turns out unique early versions
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//can be differentiated by solder mask color.
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//Final version is default and doesn't need any defines
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//#define PURPLE_KAZZO
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//#define GREEN_KAZZO //GREEN needs PURPLE defined at same time
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#ifdef GREEN_KAZZO
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void software_AHL_CLK();
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void software_AXL_CLK();
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#endif
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//=======================================================
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//History of PCB revsisions produced by InfiniteNesLives
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//=======================================================
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//
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// uncomment define if buiding for either of the first two versions
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//#define PURPLE_KAZZO
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// First printed circuit board version
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// only handful made (less than 10?)
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// Purple solder mask
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// Labeled "Kazzo PCB rev 3.0"
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// Dated 8/22/2011
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// * Only contained NES and Famicom connectors
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// * Had bug where USB data lines mixed up
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// -manually fixed during component assembly
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// * Naruko determined this should have still been v1 board
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// -due to it's overall design and conflicting with someother v3 board
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// * This was my first ever PCB design and one of the first
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// times designing something for the NES/FC. Looking
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// back at the design there were some very noob decisions...
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// * INPUT/OUTPUT differences:
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// EXP9 - PD1/LED jumper
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// when closed, PD1 controls NES EXP9 and LED
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// when open, EXP9 is floating PD1 only controls LED
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// NES EXP9 was connected to GND pin #16 on FC
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// -I must have thought that GND pin could serve
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// different purpose..
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// -Result is PD1 is shorted to GND when FC cart inserted
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// and jumper closed..
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// Believe I closed this jumper on units I shipped
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// prob should have left it open..
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// Suggested fix: leave open and ground EXP9
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// -prevents issue with LED when FC cart inserted
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// -minor draw back no access to EXP9
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// ALOG - EXP6 - DIGI jumper
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// another noob jumper decision...
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// ALOG is the MCU AREF pin which should be tied to VCC
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// -I thought it was an analog in apparently...
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// DIGI is EXP flip flop Q6 output
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// Best position for this jumper is EXP6-DIGI
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// ALOG pad should be tied to VCC with jumper..
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// Doing that would make it similar to future designs.
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// Don't think I shipped any with ALOG jumper closed
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// NES EXP6 is tied to Famicom pin 46 (Sound to RF)
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// Expansion port FlipFlop /OE - CLK
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// Aside from lame jumper design above, biggest difference
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// between this PCB version and future ones.
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// -EXP FF /OE controlled by MCU PD7
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// -EXP FF CLK controlled by MCU PC3
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// Future versions control both /OE and CLK with PD7
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// -this frees PC3 for user use
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// Both FlipFlops D i/p are driven by Data bus (PORT B)
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//
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//
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// Second printed circuit board version
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// only handful made (about a dozen?)
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// Purple solder mask
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// Labeled "Kazzo PCB rev 1.1"
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// Dated 8/22/2011
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// * Only contained NES and Famicom connectors
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// * Identical to version above aside from the following
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// * Corrected bug where USB data lines mixed up
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// * Changed silkscreen to v1.1 as suggested by naruko
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// * INPUT/OUTPUT differences:
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// -Same as version above as far as I know.
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//
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//
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// uncomment define if buiding for this versions
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//#define GREEN_KAZZO
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//
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// Third printed circuit board version
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// only handful made (about ten?) used primarily as SNES prototype
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// Green solder mask
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// Labeled "Retro programmer/dumper v1.2" "Kazzo 1.x"
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// Dated Apr 2013
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// * First version to add SNES connector along with NES & FC
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// * Removed noob jumpers from purple versions above.
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// -grouned FC pin16 as it should have been.
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// * INPUT/OUTPUT differences:
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// -EXP FF /OE still controlled by MCU PD7
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// -MCU PC7 controls both CLK on both FF's.
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// -EXP FF D inputs are PORTA
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// all other versions are driven by PORTB
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// This means you always have to clock both flipflops
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// Place desired value on PORTA/B respectively and clock with PD7
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// -PC3 is free for user use.
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// -SNES /RESET pin not controlled by PD0 (EXP0)
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// instead it's controlled by A20 (EXPFF Q4)
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// prevents putting INL SNES boards in program mode unless A20 is also low
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// pretty much makes flashing SNES boards a royal PITA/impossible
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// Suggested fix is to have PD0 (EXP0) control SNES /RESET
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// would have to free /RESET and wire to EXP0/PD0 to permit flashing/reading INL SNES board.
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//
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//
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// Fourth printed circuit board version
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// First volume PCB run ~300 copies
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// Yellow solder mask
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// Labeled "Retro programmer/dumper v1.2b" "Kazzo 1.x"
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// Dated May 2013
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// * Includes NES, Famicom, & SNES connector
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// * SNES board must be removed from case and slid all the way to right
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// * Pitch offset on SNES connector makes it difficult to connect with original SNES boards.
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// -Connector designed to only provide support for INL SNES Hi/Lo-ROM boards.
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// * Care must be excersized not to insert SNES board backwards applying reverse power.
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// * Effectively Final circuit design after lessons learned on small batches that preceeded.
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// * INPUT/OUTPUT differences:
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// -EXP FF /OE & CLK controlled by MCU PD7
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// -MCU PC7 only controls CLK on ADDR HIGH FF.
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// -EXP & ADDRHI FF D inputs both on Data bus PORTB
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// -PC3 is free for user use.
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// -SNES /RESET pin controlled by PD0 (EXP0)
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// -Retains prev ver fixes, nothing funny going on with jumpers FC GND pin #16
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//
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//
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// Fifth printed circuit board version
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// Second volume PCB run ~500 copies
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// Yellow solder mask
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// Labeled "Retro programmer/dumper v1.2b" "Kazzo 1.x"
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// Dated OCT 2014
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// * Includes NES, Famicom, & SNES connector
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// * SNES connector setup/cautions just like the prev version.
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// * No significant changes from previous version.
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// -Changed MCU clock to Crystal instead of resonator in prev ver.
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// -Added screw mount holes, although not very well placed.
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// * INPUT/OUTPUT differences:
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// -None from previous version
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//
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//
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// Sixth printed circuit board version
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// Third volume PCB run in production as of 1NOV2016
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// Orange solder mask
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// Labeled "Retro programmer/dumper v1.4" "Kazzo 1.x"
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// Dated OCT 2016
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// Addition of fancy INL logo for first time
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// * Includes NES, Famicom, & SNES connector
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// * SNES connector improvement to correct pitch issue with prev ver.
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// * Addition of PCT resettable fuse on incoming power.
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// -Provides protection to SNES boards inserted backwards.
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// * Rearrangement of BL/RUN switch and screw holes for better case design.
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// * Cut out buzzer pads (PD6) from under MCU which was never developed.
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// * INPUT/OUTPUT differences:
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// -None from previous version
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//
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//
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// STM32F070C6T6 KAZZO USB 2.0 ADAPTER board prototype
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// designed to retrofit all previous kazzo versions
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// updates to arm cortex M0 core and hardware USB 2.0
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// Green solder mask
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// Labeled "KAZZO USB 2.0 ADAPTER" "V1.P"
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// Dated JAN 2017
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// Pins out to all DIP-40 pins:
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// AVR reset -> STM reset
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// AVR BOOTLOADn -> STM BOOT0 (not sure if this actually works...)
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// AVR XTAL1/2 -> STM oscOUT/IN (PF1/0)
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//
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// ascii art board connections setup:
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//AVR PIN #40<. .-> AVR PIN #20
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// __|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|_
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// | O O O O O O O O O O O O O O O O O O O O|
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// | "KAZZO USB 2.0 ADAPTER" |
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// kazzo | programming header /\ 6pin extra port | kazzo
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// rst butn | O- /RESET / \ EMPTY -O O- PA6 | AVR PA6 "FREE"
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// CIRAM_A10| O- SWD (PA13) CIRAM A10 /STM \ EMPTY -O O- PC15 | nc
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// GND | O- GND \ 32 / 3v3 -O O- PC14 | nc
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// nc | O- SWC (PA14) \ ./ GND -O O- PA1 | nc
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// nc | O- 3v3 \/ 5v -O O- PA0 | EXP0
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// | |
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// | O O O O O O O O O O O O O O O O O O O O|
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// -------------------------------------------------------------
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// | | | | | | | | | | | | | | | | | | | |
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//AVR PIN #1<-` `-> AVR PIN #19
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//
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//
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//
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// STM32F070RBT6 "INL RETRO 6" prototype
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// completely new design with 6 connectors:
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// GBA/DMG, SNES/SFC, NES, N64, Sega gen, Famicom
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// updates to arm cortex M0 core and hardware USB 2.0
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// Green solder mask
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// Labeled "INL RETRO PROGRAMMER DUMPER V2.0P"
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// Dated MAY 2017
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// Unlike all previous version above this has direct access to most pins
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// Only exception is one Flipflop for SegaGen A17-18, 20-23, #LO_MEM, & #TIME
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// flipflop also drives SNES PA0-7
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//=============================================================================================
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//
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// PINPORT ABSTRACTION LAYER
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//
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//=============================================================================================
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//
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// The pinport abstraction layer creates definitions of generic device GPIO ports.
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// These generic ports are designed to make high level firmware generic to the
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// actual underlying hardware. The ports created have defined sizes and access rules
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// that keeps firmware from growing in complexity based on the specific hardware.
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//
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// Idea is to define ports which are available on all hardware, but also create ports
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// which may not be available to other hardwares. If the firmware is instructed to
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// perform an operation on a port that's not present, or not initialized/setup error
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// codes will be sent back to the host to designate the lack of port presence.
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//
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// STM32 GPIO registers are quite different than AVR style
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// they are more flexible/capable, but a little tricky to interface with
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// some features present on STM32 pins, but not AVR
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// - PULL-DOWN ability (and PULL-UP like AVR)
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// - Speed/Slew rate selection
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// - Open drain outputs (and push/pull like AVR)
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// - Bit set/reset registers to remove necessity of RMW operations
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// - Lockability to keep port config bits from changing until reset
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// - GPIO blocks must be provided a clock and enabled to "turn on"
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// failing to do so will cause hard faults when accessing registers!!
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//
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// All GPIO registers can be accessed in byte, halfword, or 32bit full words
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// unless otherwise noted
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//
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// GPIOx->MODER[1:0] 32bit registers control direction/type of driver
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// 00- Input (default reset state, except SWC-PA15 & SWD-PA13 default AF)
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// 01- Gen Purp Output
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// 10- Alternate func (SPI, I2C, etc)
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// 11- reserved
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// MODER[1] typically leave clear unless using AltFunc
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// MODER[0] becomes equivalent of AVR DDR
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#define MODER_OP 0x01
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#define MODER_OP_ALL 0x55555555
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#define MODER_AF 0x10
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//
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// GPIOx->OTYPER 16bit registers control driver type
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// 0- Push Pull (default reset state)
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// 1- Open Drain
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use pushpull as AVR does
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//
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// GPIOx->OSPEEDR[1:0] 32bit registers control pin driver speed/slew
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// x0- Low speed (default reset state, except SWD-PA13 default High Spd)
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// 01- Medium speed
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// 11- High speed
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use slow speed
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//
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// GPIOx->PUPDR[1:0] 32bit registers control pull-up/down resistors
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// this register is in effect even when alternate functions are enabled
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// 00- floating/disabled, no pull-up/down (default for most pins except below)
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// 01- Pull-up enabled (default SWD-PA13) also CIRAM A10
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// 10- Pull-down enabled (default SWC-PA14)
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// 11- Reserved, don't use (prob enables both which would be bad...)
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// PUPDR[0] is kinda like AVR PORT when DDR is set to INPUT, and PUPDR[1]=0
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// This ends up being a little cleaner than AVR i/o interfacing
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// Can probably just enable pull-ups on everything and leave it like that
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// -only exception being USB pins (PA11/12) better leave those floating
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//#define PUPDR_FL 0x00
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#define PUPDR_PU 0x01
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#define PUPDR_PD 0x10
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#define PUPDR_PU_ALL 0x55555555
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//
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// GPIOx->IDR 16bit register used to read current input level on pin
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// this register is read only
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//
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// GPIOx->ODR 16bit register used to set output of pin if enabled by MODER
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// this register is read/writeable
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//
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// GPIOx->BSRR 32bit register to only set/clear pins
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// BR[31:16] upper halfword is will reset/clear pin if written to '1' value
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// BS[15:00] lower halfword is will set pin if written to '1' value
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// writing 0 to any bit has no effect
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// if setting both BS register has priority (bit will be set)
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// this register is write only!
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//
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// GPIO->BRR 16bit register equivalent to upper word of BSRR register above
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// provides convinent separate BR register that doesn't need shifted
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//
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// GPIOx->LCKR 17bit register MUST BE ACCESSED in 32bit full words!!!
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// complex sequence needed to set, but once done lock config/altfunc
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// bits for that GPIO. I interpret this to mean the registers above
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// plus AF registers, exception of IDR, ODR, BSRR registers
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// Good to use this for things than we don't want to accidentally change:
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// - USB & XTAL pins come to mind as good candidates
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//
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// GPIOx->AFRL/H 2 sets of 32bit registers to determine alternate function
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// of GPIO if enabled with MODER registers. Default is AF0 at reset
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// AVR GPIO are rather simple in comparison to STM32 GPIO:
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//
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// DDRx 8bit direction register
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// Determines 'direction' of pin driver
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// set for output, clear of input
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// reads give current status of register
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//
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// PORTx 8bit output/pullup register
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// writes set/clear pin if DDR is set/OP
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// write '1' to enable pull-up if DDR is clear/IP
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// write '0' to disable pull-up if DDR is clear/IP
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// reads give current status of register
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// bit access must be done by means of RMW/shadow reg
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//
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// PINx 8bit read register
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// read when DDR is clear/IP to get current pin level
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// reading when O/P is of little use, as should be value of PORTx
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// read only register
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// ---------------------------------------------------------------------------------------
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// CONTROL PORT
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//
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// This port is present on all devices, however not all pins are present depending on device
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// Keeping this port as bit access only makes it so there is no limit to number of pins.
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// Directionality: All pins are able to be toggled between input/output individually
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// Driver: All pins indiv selectable pull-up or float for input. Output always push pull.
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// Write/Output: Bit access only, no byte/word accesses
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// Read/Input: Bit access only, returned byte/word will be zero if clear, non-zero if set
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//
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// PORT C pin definitions
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// Try not to assign one mcu pin to more than one pin in this port.
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// mcu pin can be assigned in other ports, as initializing
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// those ports will 'disable' the pin in this port.
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// if the pin has multiple purposes and would like to give
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// it different names based on the cart inserted, just create
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// multiple defines/names for the one PCn pin.
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// If a ctl pin is needed that's mapped to different mcu pins based on the board,
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// create a new control port pin and violate the first rule with caution.
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//
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// Creation of new signals:
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// 1) Create PC# -> mcupin assignment below
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// 2) map pin name to PC# which follows assignments below
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// 3) add applicable macro calls to pinport.c
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// 4) add pin name to shared_dict_pinport.h operands for simple calling from host
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// 5) add shortcut macros to pinport.h if desired
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// 6) ensure CTL PORT ENABLE macro enables new pin adequately
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//
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// ---------------------------------------------------------------------------------------
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#ifdef STM_INL6
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// PC0 "MCO" mcupinA8
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#define C0bank GPIOA
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#define C0 (8U)
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// PC1 "ROMSEL" mcupinA0
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#define C1bank GPIOA
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#define C1 (0U)
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// PC2 "PRGRW" mcupinA1
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#define C2bank GPIOA
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#define C2 (1U)
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// PC3 "FREE"
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// Not defined
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#define C3nodef
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// PC4 "CSRD" mcupinA2
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#define C4bank GPIOA
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#define C4 (2U)
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// PC5 "CSWR" mcupinA3
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#define C5bank GPIOA
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#define C5 (3U)
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// PC6 "CICE" mcupinA10
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#define C6bank GPIOA
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#define C6 (10U)
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// PC7 "AHL"
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// Not defined
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#define C7nodef
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// PC8 "EXP0" mcupinA6
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#define C8bank GPIOA
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#define C8 (6U)
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// PC9 "LED" mcupinB1
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#define C9bank GPIOB
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#define C9 (1U)
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// PC10 "IRQ" mcupinA15
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#define C10bank GPIOA
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#define C10 (15U)
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// PC11 "CIA10" mcupinA9
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#define C11bank GPIOA
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#define C11 (9U)
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// PC12 "BL"
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// Not defined
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#define C12nodef
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// PC13 "AXL"
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// Not defined
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#define C13nodef
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// PC14 "AUDL" mcupinA4
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#define C14bank GPIOA
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#define C14 (4U)
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// PC15 "AUDR" mcupinA5
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#define C15bank GPIOA
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#define C15 (5U)
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// PC16 "CIN" mcupinA7
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#define C16bank GPIOA
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#define C16 (7U)
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// PC17 "SWD" mcupinA13
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#define C17bank GPIOA
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#define C17 (13U)
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// PC18 "SWC" mcupinA14
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#define C18bank GPIOA
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#define C18 (14U)
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// PC19 "AFL" mcupinB0
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#define C19bank GPIOB
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#define C19 (0U)
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// PC20 "COUT" mcupinD2
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#define C20bank GPIOD
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#define C20 (2U)
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// PC21 "FCAPU" double mapping of AUDR
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#define C21bank C15bank
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#define C21 C15
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/* NEED MORE UNIQUE names for these pins to not conflict with Data port definitions...
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// PCxx "D8" mcupinB10
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#define Cxxbank GPIOB
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|
#define Cxx (10U)
|
|
|
|
// PC22 "D9" mcupinB11
|
|
#define C22bank GPIOB
|
|
#define C22 (11U)
|
|
|
|
// PC23 "D10" mcupinB12
|
|
#define C23bank GPIOB
|
|
#define C23 (12U)
|
|
|
|
// PC24 "D11" mcupinB13
|
|
#define C24bank GPIOB
|
|
#define C24 (13U)
|
|
|
|
// PC25 "D12" mcupinB14
|
|
#define C25bank GPIOB
|
|
#define C25 (14U)
|
|
|
|
// PC26 "D13" mcupinB15
|
|
#define C26bank GPIOB
|
|
#define C26 (15U)
|
|
*/
|
|
|
|
|
|
#define RCC_AHBENR_CTL (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIODEN)
|
|
#define RCC_AHBENR_ADDR RCC_AHBENR_GPIOCEN
|
|
#define RCC_AHBENR_HADDR (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN)
|
|
#define RCC_AHBENR_DATA RCC_AHBENR_GPIOBEN
|
|
#define RCC_AHBENR_EXP (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN)
|
|
|
|
|
|
#endif //STM_INL6
|
|
|
|
#ifdef STM_ADAPTER
|
|
|
|
// PC0 "MCO" mcupinA3
|
|
#define C0bank GPIOA
|
|
#define C0 (3U)
|
|
|
|
// PC1 "ROMSEL" mcupinA4
|
|
#define C1bank GPIOA
|
|
#define C1 (4U)
|
|
|
|
// PC2 "PRGRW" mcupinA5
|
|
#define C2bank GPIOA
|
|
#define C2 (5U)
|
|
|
|
// PC3 "FREE" mcupinA6
|
|
#define C3bank GPIOA
|
|
#define C3 (6U)
|
|
#ifdef PURPLE_KAZZO
|
|
#define C3nodef //assigned to PAXL instead which is tied to AXL /OE in software
|
|
#endif
|
|
|
|
// PC4 "CSRD" mcupinA7
|
|
#define C4bank GPIOA
|
|
#define C4 (7U)
|
|
|
|
// PC5 "CSWR" mcupinB0
|
|
#define C5bank GPIOB
|
|
#define C5 (0U)
|
|
|
|
// PC6 "CICE" mcupinA10
|
|
#define C6bank GPIOA
|
|
#define C6 (10U)
|
|
|
|
// PC7 "AHL" mcupinB1
|
|
#define C7bank GPIOB
|
|
#define C7 (1U)
|
|
|
|
// PC8 "EXP0" mcupinA0
|
|
#define C8bank GPIOA
|
|
#define C8 (0U)
|
|
|
|
// PC9 "LED" mcupinC13
|
|
#define C9bank GPIOC
|
|
#define C9 (13U)
|
|
|
|
// PC10 "IRQ" mcupinA15
|
|
#define C10bank GPIOA
|
|
#define C10 (15U)
|
|
|
|
// PC11 "CIA10" mcupinA13
|
|
#define C11bank GPIOA
|
|
#define C11 (13U)
|
|
|
|
// PC12 "BL"
|
|
// Not defined
|
|
#define C12nodef
|
|
|
|
// PC13 "AXL" mcupinA2
|
|
#define C13bank GPIOA
|
|
#define C13 (2U)
|
|
|
|
// PC14 "AUDL"
|
|
// Not defined
|
|
#define C14nodef
|
|
|
|
// PC15 "AUDR"
|
|
// Not defined
|
|
#define C15nodef
|
|
|
|
// PC16 "CIN"
|
|
// Not defined
|
|
#define C16nodef
|
|
|
|
// PC17 "SWD" mcupinA13
|
|
// Not defined due to shared with CIRAM A10
|
|
#define C17nodef
|
|
|
|
// PC18 "SWC" mcupinA14
|
|
#define C18bank GPIOA
|
|
#define C18 (14U)
|
|
|
|
// PC19 "AFL"
|
|
// Not defined
|
|
#define C19nodef
|
|
|
|
// PC20 "COUT"
|
|
// Not defined
|
|
#define C20nodef
|
|
|
|
// PC21 "FCAPU" double mapping of EXP0
|
|
#define C21bank C8bank
|
|
#define C21 C8
|
|
|
|
|
|
#define RCC_AHBENR_CTL (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOCEN)
|
|
#define RCC_AHBENR_ADDR (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN)
|
|
#define RCC_AHBENR_DATA RCC_AHBENR_GPIOBEN
|
|
|
|
#endif //STM_ADAPTER
|
|
|
|
|
|
#ifdef AVR_KAZZO
|
|
|
|
// PC0 "MCO" mcupinC0
|
|
#define C0bank GPIOC
|
|
#define C0 (0U)
|
|
|
|
// PC1 "ROMSEL" mcupinC1
|
|
#define C1bank GPIOC
|
|
#define C1 (1U)
|
|
|
|
// PC2 "PRGRW" mcupinC2
|
|
#define C2bank GPIOC
|
|
#define C2 (2U)
|
|
|
|
// PC3 "FREE" mcupinC3
|
|
#define C3bank GPIOC
|
|
#define C3 (3U)
|
|
#ifdef PURPLE_KAZZO
|
|
#define C3nodef //assigned to PAXL instead which is tied to AXL /OE in software
|
|
#endif
|
|
|
|
// PC4 "CSRD" mcupinC4
|
|
#define C4bank GPIOC
|
|
#define C4 (4U)
|
|
|
|
// PC5 "CSWR" mcupinC5
|
|
#define C5bank GPIOC
|
|
#define C5 (5U)
|
|
|
|
// PC6 "CICE" mcupinC6
|
|
#define C6bank GPIOC
|
|
#define C6 (6U)
|
|
|
|
// PC7 "AHL" mcupinC7
|
|
#define C7bank GPIOC
|
|
#define C7 (7U)
|
|
|
|
// PC8 "EXP0" mcupinD0
|
|
#define C8bank GPIOD
|
|
#define C8 (0U)
|
|
|
|
// PC9 "LED" mcupinD1
|
|
#define C9bank GPIOD
|
|
#define C9 (1U)
|
|
|
|
// PC10 "IRQ" mcupinD3
|
|
#define C10bank GPIOD
|
|
#define C10 (3U)
|
|
|
|
// PC11 "CIA10" mcupinD5
|
|
#define C11bank GPIOD
|
|
#define C11 (5U)
|
|
|
|
// PC12 "BL" mcupinD6
|
|
#define C12bank GPIOD
|
|
#define C12 (6U)
|
|
|
|
// PC13 "AXL" mcupinD7 //PURPLE KAZZO uses this for /OE only
|
|
#define C13bank GPIOD
|
|
#define C13 (7U)
|
|
|
|
// PC14 "AUDL"
|
|
// not defined
|
|
#define C14nodef
|
|
|
|
// PC15 "AUDR"
|
|
// not defined
|
|
#define C15nodef
|
|
|
|
// PC16 "CIN"
|
|
// not defined
|
|
#define C16nodef
|
|
|
|
// PC17 "SWD"
|
|
// not defined
|
|
#define C17nodef
|
|
|
|
// PC18 "SWC"
|
|
// not defined
|
|
#define C18nodef
|
|
|
|
// PC19 "AFL"
|
|
// not defined
|
|
#define C19nodef
|
|
|
|
// PC20 "COUT"
|
|
// not defined
|
|
#define C20nodef
|
|
|
|
// PC21 "FCAPU" double mapping of EXP0
|
|
#define C21bank C8bank
|
|
#define C21 C8
|
|
|
|
|
|
#endif //AVR_KAZZO
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// PORT C pin mappings
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// PC0-13 are defined based on majority of avr kazzos PORTC-PORTD
|
|
// PC0 "MCO" mcu clock out M2/phi2, Sysclk, etc
|
|
#define MCO C0
|
|
#define MCObank C0bank
|
|
|
|
// PC1 "ROMSEL" Cartridge rom enable
|
|
#define ROMSEL C1
|
|
#define ROMSELbank C1bank
|
|
|
|
// PC2 "PRGRW" NES CPU R/W signal
|
|
#define PRGRW C2
|
|
#define PRGRWbank C2bank
|
|
|
|
// PC3 "FREE" purple kazzo EXP flipflop latch, FREE on most kazzos
|
|
#define FREE C3
|
|
#define FREEbank C3bank
|
|
|
|
// PC4 "CSRD" NES CHR/SNES /RD
|
|
#define CSRD C4
|
|
#define CSRDbank C4bank
|
|
|
|
// PC5 "CSWR" NES CHR/SNES /WR
|
|
#define CSWR C5
|
|
#define CSWRbank C5bank
|
|
|
|
// PC6 "CICE" NES CIRAM /CE
|
|
#define CICE C6
|
|
#define CICEbank C6bank
|
|
|
|
// PC7 "AHL" ADDR HI Latch
|
|
#define AHL C7
|
|
#define AHLbank C7bank
|
|
|
|
// PC8 "EXP0" NES EXP0, FC APU sound, cart-console /RESET
|
|
#define EXP0 C8
|
|
#define EXP0bank C8bank
|
|
|
|
// PC9 "LED" kazzos tied this to NES EXP9, INL6 connects to CIC CLK
|
|
#define LED C9
|
|
#define LEDbank C9bank
|
|
|
|
// PC10 "IRQ" console CPU interrupt from cart
|
|
#define IRQ C10
|
|
#define IRQbank C10bank
|
|
|
|
// PC11 "CIA10" NES CIRAM A10
|
|
#define CIA10 C11
|
|
#define CIA10bank C11bank
|
|
|
|
// PC12 "BL" Bootloader pin
|
|
#define BL C12
|
|
#define BLbank C12bank
|
|
|
|
// PC13 "AXL" EXP FF latch and /OE, purple kazzos this was only /OE
|
|
#define AXL C13
|
|
#define AXLbank C13bank
|
|
|
|
// INLretro6 adds following pins
|
|
// PC14 "AUDL" cart audio
|
|
#define AUDL C14
|
|
#define AUDLbank C14bank
|
|
|
|
// PC15 "AUDR" cart audio
|
|
#define AUDR C15
|
|
#define AUDRbank C15bank
|
|
|
|
// PC16 "CIN" CIC data in
|
|
#define CIN C16
|
|
#define CINbank C16bank
|
|
|
|
// PC17 "SWD" mcu debug
|
|
#define SWD C17
|
|
#define SWDbank C17bank
|
|
|
|
// PC18 "SWC" mcu debug
|
|
#define SWC C18
|
|
#define SWCbank C18bank
|
|
|
|
// PC19 "AFL" flipflop addr expansion for FF0-7
|
|
#define AFL C19
|
|
#define AFLbank C19bank
|
|
|
|
// PC20 "COUT" CIC data out
|
|
#define COUT C20
|
|
#define COUTbank C20bank
|
|
|
|
// PC21 "FCAPU" cart audio in
|
|
#define FCAPU C21
|
|
#define FCAPUbank C21bank
|
|
|
|
// INLretro6 gains direct control over NES EXP port and is used for N64 control pins:
|
|
/*
|
|
// PCxx "D8"
|
|
#define D8 Cxx
|
|
#define D8bank Cxxbank
|
|
|
|
// PC22 "D9"
|
|
#define D9 C22
|
|
#define D9bank C22bank
|
|
|
|
// PC23 "D10"
|
|
#define D10 C23
|
|
#define D10bank C23bank
|
|
|
|
// PC24 "D11"
|
|
#define D11 C24
|
|
#define D11bank C24bank
|
|
|
|
// PC25 "D12"
|
|
#define D12 C25
|
|
#define D12bank C25bank
|
|
|
|
// PC26 "D13"
|
|
#define D12 C26
|
|
#define D12bank C26bank
|
|
|
|
// PC27 "D14"
|
|
#define D12 C27
|
|
#define D12bank C27bank
|
|
|
|
// D15 & D16 are defined as CICE/CIA10 above
|
|
*/
|
|
|
|
#ifdef STM_CORE
|
|
|
|
#define CTL_IP_PU(bank, pin) bank->MODER &= ~(MODER_OP<<(pin*2)); bank->PUPDR |= (PUPDR_PU<<(pin*2))
|
|
#define CTL_IP_FL(bank, pin) bank->MODER &= ~(MODER_OP<<(pin*2)); bank->PUPDR &= ~(PUPDR_PU<<(pin*2))
|
|
#define CTL_OP(bank, pin) bank->MODER |= (MODER_OP<<(pin*2))
|
|
#define CTL_SET_LO(bank, pin) bank->BRR = 1<<pin
|
|
#define CTL_SET_HI(bank, pin) bank->BSRR = 1<<pin
|
|
#define CTL_RD(bank, pin, val) val = (bank->IDR & (1<<pin))
|
|
//NOTE: STM registers are 16bit "halfwords" so must provide a 16bit val
|
|
|
|
#define CTL_ENABLE() RCC->AHBENR |= RCC_AHBENR_CTL
|
|
|
|
#endif //STM_CORE
|
|
|
|
#ifdef AVR_CORE
|
|
|
|
#define CTL_IP_PU(bank, pin) bank->DDR &= ~(1<<pin); bank->PORT |= (1<<pin)
|
|
#define CTL_IP_FL(bank, pin) bank->DDR &= ~(1<<pin); bank->PORT &= ~(1<<pin)
|
|
#define CTL_OP(bank, pin) bank->DDR |= (1<<pin)
|
|
#define CTL_SET_LO(bank, pin) bank->PORT &= ~(1<<pin)
|
|
#define CTL_SET_HI(bank, pin) bank->PORT |= (1<<pin)
|
|
#define CTL_RD(bank, pin, val) val = (uint16_t) (bank->PIN & (1<<pin))
|
|
|
|
#define CTL_ENABLE() //nothing to be done for AVR
|
|
|
|
|
|
#endif //AVR_CORE
|
|
|
|
|
|
// CONTROL PORT MACROS to simplify flipflop operations
|
|
//
|
|
|
|
#ifndef STM_INL6
|
|
|
|
#ifdef GREEN_KAZZO
|
|
#define AHL_CLK() software_AHL_CLK()
|
|
#define AXL_CLK() software_AXL_CLK()
|
|
#elif defined PURPLE_KAZZO
|
|
#define AHL_CLK() CTL_SET_HI(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL)
|
|
#define AXL_CLK() CTL_SET_HI(FREEbank, FREE); CTL_SET_LO(FREEbank, FREE)
|
|
#else
|
|
#define AHL_CLK() CTL_SET_HI(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL)
|
|
#define AXL_CLK() CTL_SET_HI(AXLbank, AXL); CTL_SET_LO(AXLbank, AXL)
|
|
#endif
|
|
#endif
|
|
|
|
// ---------------------------------------------------------------------------------------
|
|
// DATA PORT 8bit
|
|
//
|
|
// This port is present on all devices
|
|
// Directionality: All pins are bidirectional controlled as a whole
|
|
// Driver: All pins are push-pull, and unknown floating/pull-up when input
|
|
// main reason to be unknown is AVR uses PORT for pull-up enable
|
|
// don't want to require re-enabling pullups for every data access
|
|
// STM32 are default to pull-up, AVR requires manually pulling up
|
|
// by calling DATA_IP_PU() if pullups required, otherwise unknown
|
|
// Write/Output: Byte access only, no bit accesses. Must be returned to input after read!
|
|
// Read/Input: Default condition, byte access only
|
|
//
|
|
// ---------------------------------------------------------------------------------------
|
|
//
|
|
#ifdef STM_INL6
|
|
|
|
//All 8bits are on GPIOB inorder, but mapped to bits9-2 for 5v tolerance
|
|
//I get why I designed it that way so D8-13 could follow in order..
|
|
//But with D8-15 required to be broken up anyways, perhaps it would have
|
|
//made more sense to map D0-7 to bits 9-15 so byte access could be performed
|
|
//without shifting on Data7-0...
|
|
//IDK if I will reroute the board for production or not... Only other way to
|
|
//do it senisbly really makes a mess of the upper byte of Data
|
|
#define Dbank GPIOB
|
|
|
|
//IP and OP assume MODER[1] is clear (ie not set to Alt Func)
|
|
//also assume PUPDR is reset default floating
|
|
#define DATA_IP_PU() Dbank->MODER &= ~(MODER_OP_ALL & 0x000FFFF0); Dbank->PUPDR |= (PUPDR_PU_ALL & 0x000FFFF0)
|
|
#define DATA_IP() Dbank->MODER &= ~(MODER_OP_ALL & 0x000FFFF0)
|
|
#define DATA_OP() Dbank->MODER |= (MODER_OP_ALL & 0x000FFFF0)
|
|
#define DATA_SET(data) Dbank->ODR = (Dbank->ODR & 0xFC03) | (data<<2)
|
|
#define DATA_RD(data) data = (Dbank->IDR>>2) & 0x00FF
|
|
|
|
#define DATA_EN_CLK() RCC->AHBENR |= RCC_AHBENR_DATA
|
|
#define DATA_ENABLE() DATA_EN_CLK(); DATA_IP_PU();
|
|
|
|
|
|
#endif //STM_INL6
|
|
|
|
#ifdef STM_ADAPTER
|
|
|
|
//All 8bits are on GPIOB in order, but mapped to bits15-8
|
|
#define Dbank GPIOB
|
|
|
|
//IP and OP assume MODER[1] is clear (ie not set to Alt Func)
|
|
//also assume PUPDR is reset default floating
|
|
#define DATA_IP_PU() Dbank->MODER &= ~(MODER_OP_ALL & 0xFFFF0000); Dbank->PUPDR |= (PUPDR_PU_ALL & 0xFFFF0000)
|
|
#define DATA_IP() Dbank->MODER &= ~(MODER_OP_ALL & 0xFFFF0000)
|
|
#define DATA_OP() Dbank->MODER |= (MODER_OP_ALL & 0xFFFF0000)
|
|
//TODO create byte wide port structs to grant byte accesses so doesn't need shifted
|
|
#define DATA_SET(data) Dbank->ODR = (Dbank->ODR & 0x00FF) | (data<<8)
|
|
#define DATA_RD(data) data = (Dbank->IDR>>8) & 0x00FF
|
|
|
|
#define DATA_EN_CLK() RCC->AHBENR |= RCC_AHBENR_DATA
|
|
#define DATA_ENABLE() DATA_EN_CLK(); DATA_IP_PU()
|
|
|
|
#endif //STM_ADAPTER
|
|
|
|
#ifdef AVR_KAZZO
|
|
|
|
//All 8bits are on GPIOB aligned perfectly
|
|
#define Dbank GPIOB
|
|
|
|
#define DATA_SET(data) Dbank->PORT = data
|
|
#define DATA_IP_PU() Dbank->DDR = 0x00; DATA_SET(0xFF)
|
|
#define DATA_IP() Dbank->DDR = 0x00
|
|
#define DATA_OP() Dbank->DDR = 0xFF
|
|
#define DATA_RD(data) data = Dbank->PIN
|
|
|
|
#define DATA_ENABLE() DATA_IP_PU()
|
|
|
|
#endif //AVR_KAZZO
|
|
|
|
|
|
// ---------------------------------------------------------------------------------------
|
|
// ADDRESS PORT 16bit
|
|
//
|
|
// This port is present on all devices
|
|
// Directionality: All pins are forced output
|
|
// Driver: All pins are push-pull
|
|
// Write/Output: Byte/half word access only, no bit accesses
|
|
// Read/Input: Not supported
|
|
//
|
|
// ---------------------------------------------------------------------------------------
|
|
|
|
#ifdef STM_INL6
|
|
|
|
//All 16bits are on GPIOC in perfect alignment
|
|
#define Abank GPIOC
|
|
|
|
#define ADDR_PU() Abank->PUPDR |= PUPDR_PU_ALL
|
|
#define ADDR_IP() Abank->MODER &= ~MODER_OP_ALL
|
|
#define ADDR_OP() Abank->MODER |= MODER_OP_ALL
|
|
#define ADDRL(low) Abank->ODR = (Abank->ODR & 0xFF00) | low
|
|
#define ADDRH(high) Abank->ODR = (Abank->ODR & 0x00FF) | (high<<8)
|
|
#define ADDR_SET(hword) Abank->ODR = hword
|
|
|
|
#define ADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_ADDR
|
|
#define ADDR_ENABLE() ADDR_EN_CLK(); ADDR_OP()
|
|
|
|
#endif //STM_INL6
|
|
|
|
#ifdef STM_ADAPTER
|
|
|
|
// A15-8 are behind AHL flipflop
|
|
// A7-6 are on GPIO A9-8
|
|
// A5-0 are on GPIO A7-2
|
|
#define A76bank GPIOA
|
|
#define A50bank GPIOB
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#define ADDR_PU() A76bank->PUPDR |= (PUPDR_PU_ALL & 0x000F0000); A50bank->PUPDR |= (PUPDR_PU_ALL & 0x0000FFF0)
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#define ADDR_IP() A76bank->MODER &= ~(MODER_OP_ALL & 0x000F0000); A50bank->MODER &= ~(MODER_OP_ALL & 0x0000FFF0)
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#define ADDR_OP() A76bank->MODER |= (MODER_OP_ALL & 0x000F0000); A50bank->MODER |= (MODER_OP_ALL & 0x0000FFF0)
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//WARNING!!! Don't use pre/post increment on passed in argument as macro expands to double inc/decrement variable!!!
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#define ADDRL(low) A76bank->ODR = (A76bank->ODR & 0xFCFF) | ((low & 0xC0)<<2);A50bank->ODR = (A50bank->ODR & 0xFF03) | ((low & 0x3F)<<2)
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//clocks must be initialized, Data bus clear
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#define ADDRH(high) DATA_OP(); DATA_SET(high); AHL_CLK(); DATA_IP()
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#define ADDR_SET(hword) ADDRL(hword); ADDRH(hword>>8)
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#define ADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_ADDR
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#define ADDR_EN_FF() CTL_OP(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL)
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#define ADDR_ENABLE() DATA_ENABLE(); ADDR_EN_CLK(); ADDR_EN_FF(); ADDR_OP()
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#endif //STM_ADAPTER
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#ifdef AVR_KAZZO
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// A15-8 are behind AHL flipflop
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// A7-0 are on GPIOA perfectly aligned
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#define ALbank GPIOA
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#define ADDR_PU() ALbank->PORT = 0xFF
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#define ADDR_IP() ALbank->DDR = 0x00
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#define ADDR_OP() ALbank->DDR = 0xFF
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#define ADDRL(low) GPIOA->PORT = low
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//clocks must be initialized, Data bus clear
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#define ADDRH(high) DATA_OP(); DATA_SET(high); AHL_CLK(); DATA_IP();
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#define ADDR_SET(hword) ADDRL(hword); ADDRH(hword>>8)
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#define ADDR_EN_FF() CTL_OP(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL)
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#define ADDR_ENABLE() DATA_ENABLE(); ADDR_EN_FF(); ADDR_OP();
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#endif //AVR_KAZZO
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// ---------------------------------------------------------------------------------------
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// EXPANSION PORT 8bit pins #1-8
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//
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// This port is present on all devices but implemented differently.
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// This port is primarily targeted as a NES cartridge port to connect to EXP1-8
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// EXP0 has it's own dedicated pin in CTL PORT, EXP9 is dual purposed with LED on AVR/adapters
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// AVR & ADAPTER connect EXP6 to Famicom RF audio (cart output)
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// INL6 dual purposes EXP6, 8, & 9 with CLT PORT AUDL, SWCLK, & AUDR respectively
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// Need some sort of interlock to ensure CTL PORT & EXP PORT don't stop on eachother's shared pins
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// Extra macros are needed to make this port compatible on early versions of AVR KAZZO
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// AVR & Adapter have access via 8x Flipflop
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// -these devices also map these pins to A16-23
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// INL6 has direct pin access
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// -these pins also act as Data8-15 for Sega Genesis
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// -has separate pins dedicated to A16-23
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// Directionality: All pins are forced output, or tristate. This maintains compatability
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// between all devices
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// Driver: All pins are push-pull, AVR & STM ADAPTER drive with 5v signals, INL6 drives with 3.3v
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// Write/Output: Byte access only, no bit accesses
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// Read/Input: Not supported
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//
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// ---------------------------------------------------------------------------------------
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#ifdef STM_INL6
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//pins1-5 = GPIOB10-14 (D8-12), pin6 = GPIOA4 (AUDL), pin7 = GPIOB15 (D13), pin8 = GPIOA14 (SWCLK)
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//these defines are quite the mess currently due to pins all over the place
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//there is no real benefit to defining this port as byte wide but defining them this way 'degrades'
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//them to the same quality as AVR making all devices mostly compatible.
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//These can be redefined as CONTROL PORT for simpler pin granuarity access
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#define E157bank GPIOB
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#define E68bank GPIOA
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#define EXP_PU() E157bank->PUPDR |= (PUPDR_PU_ALL & 0xFFF00000); E68bank->PUPDR |= (PUPDR_PU_ALL & 0x30000300)
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#define EXP_IP() E157bank->MODER &=~(MODER_OP_ALL & 0xFFF00000); E68bank->MODER &=~(MODER_OP_ALL & 0x30000300)
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#define EXP_OP() E157bank->MODER |= (MODER_OP_ALL & 0xFFF00000); E68bank->MODER |= (MODER_OP_ALL & 0x30000300)
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//not sure these bit shift accesses will work if the value passed in is a uint8_t variable...
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#define EXP_SET(val) E157bank->ODR = ((E157bank->ODR & 0x03FF) | (val<<10 & 0x7C00) | (val<<9 & 0x8000)); E68bank->ODR = ((E68bank->ODR & 0xBFEF) | (val>>1 & 0x0010) | (val<<7 & 0x4000))
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#define EXP_EN_CLK() RCC->AHBENR |= RCC_AHBENR_EXP
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#define EXP_ENABLE() ADDR_EN_CLK(); EXP_OP()
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#define EXP_DISABLE() EXP_PU(); EXP_IP()
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//end STM_INL6
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#else //AVR_KAZZO or STM_ADAPTER
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// EXP1-8 are behind AXL flipflop
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|
|
|
//clocks must be initialized, Data bus clear
|
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#define EXP_SET(val) DATA_OP(); DATA_SET(val); AXL_CLK(); DATA_IP()
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|
|
#ifdef PURPLE_KAZZO
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#define EXP_EN_FF() CTL_OP(AXLbank, AXL); CTL_SET_LO(AXLbank, AXL); CTL_OP(FREEbank, FREE); CTL_SET_LO(FREEbank, FREE);
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#define EXP_DISABLE() CTL_IP_PU(AXLbank, AXL); CTL_IP_PU(FREEbank, FREE)
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#else
|
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#define EXP_EN_FF() CTL_OP(AXLbank, AXL); CTL_SET_LO(AXLbank, AXL)
|
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#define EXP_DISABLE() CTL_IP_PU(AXLbank, AXL)
|
|
#endif
|
|
|
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#define EXP_ENABLE() DATA_ENABLE(); CTL_ENABLE(); EXP_EN_FF()
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|
|
|
#endif //AVR_KAZZO or STM_ADAPTER
|
|
|
|
|
|
// ---------------------------------------------------------------------------------------
|
|
// HIGH ADDRESS PORT 8bits A16-23
|
|
//
|
|
// This port is present on all devices
|
|
// Restrictions: CANNOT be used when EXPANSION PORT is enabled
|
|
// CIRAM_A10 & CIRAM /CE cannot be used on CONTROL PORT
|
|
// Directionality: All pins are forced output
|
|
// Driver: All pins are push-pull
|
|
// Write/Output: Byte access only, no bit accesses
|
|
// Read/Input: Not supported
|
|
//
|
|
// INL6 dual purposes A22-23 for CIRAM_A10 & CIRAM_CE respectively
|
|
// EXP1-5, & 7 are mapped to A16-21 respectively
|
|
//
|
|
// AVR_KAZZO & STM_ADATPER use dual purpose the EXPANSION PORT for this PORT
|
|
// EXP1-8 map to A16-23 respectively
|
|
//
|
|
// ---------------------------------------------------------------------------------------
|
|
|
|
#ifdef STM_INL6
|
|
|
|
//A16-21 are on PB10-15 these also map to EXP1-5, & 7
|
|
//A22-23 are on PA9-10 these also map to CIRAM A10 & CIRAM /CE respectively
|
|
#define A16_21bank GPIOB
|
|
#define A22_23bank GPIOA
|
|
|
|
#define HADDR_PU() A16_21bank->PUPDR |= (PUPDR_PU_ALL & 0xFFF00000); A22_23bank->PUPDR |= (PUPDR_PU_ALL & 0x0003C000)
|
|
#define HADDR_IP() A16_21bank->MODER &=~(MODER_OP_ALL & 0xFFF00000); A22_23bank->MODER &=~(MODER_OP_ALL & 0x0003C000)
|
|
#define HADDR_OP() A16_21bank->MODER |= (MODER_OP_ALL & 0xFFF00000); A22_23bank->MODER |= (MODER_OP_ALL & 0x0003C000)
|
|
|
|
#define HADDR_SET(val) A16_21bank->ODR = ((A16_21bank->ODR&0x03FF) | (val<<10 & 0xFC00)); A22_23bank->ODR = ((A22_23bank->ODR & 0xF9FF) | (val<<3 & 0x0600))
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|
|
|
#define HADDR_EN_CLK() RCC->AHBENR |= RCC_AHBENR_HADDR
|
|
#define HADDR_ENABLE() HADDR_EN_CLK(); HADDR_OP()
|
|
#define HADDR_DISABLE() HADDR_PU(); HADDR_IP()
|
|
|
|
//end STM_INL6
|
|
#else //AVR_KAZZO or STM_ADAPTER
|
|
|
|
|
|
// ADDR16-23 are behind AXL flipflop
|
|
|
|
//clocks must be initialized, Data bus clear
|
|
#define HADDR_SET(val) EXP_SET(val)
|
|
|
|
#define HADDR_EN_FF() EXP_EN_FF()
|
|
#define HADDR_ENABLE() EXP_ENABLE()
|
|
#define HADDR_DISABLE() EXP_DISABLE()
|
|
|
|
#endif //AVR_KAZZO or STM_ADAPTER
|
|
|
|
|
|
#endif
|