223 lines
7.0 KiB
C
223 lines
7.0 KiB
C
#ifndef _pinport_h
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#define _pinport_h
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#include "pinport_al.h"
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#include "shared_errors.h"
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#include "shared_dict_pinport.h"
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uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata );
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// used for a very short delay
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#define NOP() do { __asm__ __volatile__ ("nop"); } while (0)
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////////////////////////////////
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// CONTROL (CTL) PORT PINS
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////////////////////////////////
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// PC0 "M2"
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#define M2_IP_PU() CTL_IP_PU(M2bank, M2)
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#define M2_IP_FL() CTL_IP_FL(M2bank, M2)
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#define M2_OP() CTL_OP(M2bank, M2)
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#define M2_LO() CTL_SET_LO(M2bank, M2)
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#define M2_HI() CTL_SET_HI(M2bank, M2)
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#define M2_RD(val) CTL_RD(M2bank, M2, val)
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// PC1 "ROMSEL"
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#define ROMSEL_IP_PU() CTL_IP_PU(ROMSELbank, ROMSEL)
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#define ROMSEL_IP_FL() CTL_IP_FL(ROMSELbank, ROMSEL)
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#define ROMSEL_OP() CTL_OP(ROMSELbank, ROMSEL)
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#define ROMSEL_LO() CTL_SET_LO(ROMSELbank, ROMSEL)
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#define ROMSEL_HI() CTL_SET_HI(ROMSELbank, ROMSEL)
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#define ROMSEL_RD(val) CTL_RD(ROMSELbank, ROMSEL, val)
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// same pin: N64 ALE_L
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#define ALE_L_OP() CTL_OP(ROMSELbank, ROMSEL)
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#define ALE_L_IP_PU() CTL_IP_PU(ROMSELbank, ROMSEL)
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#define ALE_L_LO() CTL_SET_LO(ROMSELbank, ROMSEL)
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#define ALE_L_HI() CTL_SET_HI(ROMSELbank, ROMSEL)
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// PC2 "PRGRW"
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#define PRGRW_IP_PU() CTL_IP_PU(PRGRWbank, PRGRW)
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#define PRGRW_IP_FL() CTL_IP_FL(PRGRWbank, PRGRW)
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#define PRGRW_OP() CTL_OP(PRGRWbank, PRGRW)
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#define PRGRW_LO() CTL_SET_LO(PRGRWbank, PRGRW)
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#define PRGRW_HI() CTL_SET_HI(PRGRWbank, PRGRW)
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#define PRGRW_RD(val) CTL_RD(PRGRWbank, PRGRW, val)
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// same pin: N64 ALE_H
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#define ALE_H_IP_PU() CTL_IP_PU(PRGRWbank, PRGRW)
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#define ALE_H_OP() CTL_OP(PRGRWbank, PRGRW)
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#define ALE_H_LO() CTL_SET_LO(PRGRWbank, PRGRW)
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#define ALE_H_HI() CTL_SET_HI(PRGRWbank, PRGRW)
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// PC3 "FREE"
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#ifndef C3nodef
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#define FREE_IP_PU() CTL_IP_PU(FREEbank, FREE)
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#define FREE_IP_FL() CTL_IP_FL(FREEbank, FREE)
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#define FREE_OP() CTL_OP(FREEbank, FREE)
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#define FREE_LO() CTL_SET_LO(FREEbank, FREE)
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#define FREE_HI() CTL_SET_HI(FREEbank, FREE)
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#define FREE_RD(val) CTL_RD(FREEbank, FREE, val)
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#endif
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// PC4 "CSRD"
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#define CSRD_IP_PU() CTL_IP_PU(CSRDbank, CSRD)
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#define CSRD_IP_FL() CTL_IP_FL(CSRDbank, CSRD)
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#define CSRD_OP() CTL_OP(CSRDbank, CSRD)
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#define CSRD_LO() CTL_SET_LO(CSRDbank, CSRD)
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#define CSRD_HI() CTL_SET_HI(CSRDbank, CSRD)
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#define CSRD_RD(val) CTL_RD(CSRDbank, CSRD, val)
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// PC5 "CSWR"
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#define CSWR_IP_PU() CTL_IP_PU(CSWRbank, CSWR)
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#define CSWR_IP_FL() CTL_IP_FL(CSWRbank, CSWR)
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#define CSWR_OP() CTL_OP(CSWRbank, CSWR)
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#define CSWR_LO() CTL_SET_LO(CSWRbank, CSWR)
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#define CSWR_HI() CTL_SET_HI(CSWRbank, CSWR)
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#define CSWR_RD(val) CTL_RD(CSWRbank, CSWR, val)
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// PC6 "CICE"
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#define CICE_IP_PU() CTL_IP_PU(CICEbank, CICE)
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#define CICE_IP_FL() CTL_IP_FL(CICEbank, CICE)
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#define CICE_OP() CTL_OP(CICEbank, CICE)
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#define CICE_LO() CTL_SET_LO(CICEbank, CICE)
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#define CICE_HI() CTL_SET_HI(CICEbank, CICE)
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#define CICE_RD(val) CTL_RD(CICEbank, CICE, val)
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// PC7 "AHL"
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#ifndef C7nodef
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#define AHL_IP_PU() CTL_IP_PU(AHLbank, AHL)
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#define AHL_IP_FL() CTL_IP_FL(AHLbank, AHL)
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#define AHL_OP() CTL_OP(AHLbank, AHL)
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#define AHL_LO() CTL_SET_LO(AHLbank, AHL)
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#define AHL_HI() CTL_SET_HI(AHLbank, AHL)
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#define AHL_RD(val) CTL_RD(AHLbank, AHL, val)
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#endif
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// PC8 "EXP0"
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#define EXP0_IP_PU() CTL_IP_PU(EXP0bank, EXP0)
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#define EXP0_IP_FL() CTL_IP_FL(EXP0bank, EXP0)
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#define EXP0_OP() CTL_OP(EXP0bank, EXP0)
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#define EXP0_LO() CTL_SET_LO(EXP0bank, EXP0)
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#define EXP0_HI() CTL_SET_HI(EXP0bank, EXP0)
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#define EXP0_RD(val) CTL_RD(EXP0bank, EXP0, val)
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#ifdef STM_CORE
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#define EXP0_OD() CTL_OD(EXP0bank, EXP0)
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#define EXP0_PP() CTL_PP(EXP0bank, EXP0)
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#endif
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// PC9 "LED"
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#define LED_IP_PU() CTL_IP_PU(LEDbank, LED)
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#define LED_IP_FL() CTL_IP_FL(LEDbank, LED)
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#define LED_OP() CTL_OP(LEDbank, LED)
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#define LED_LO() CTL_SET_LO(LEDbank, LED)
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#define LED_HI() CTL_SET_HI(LEDbank, LED)
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#define LED_RD(val) CTL_RD(LEDbank, LED, val)
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// PC10 "IRQ"
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#define IRQ_IP_PU() CTL_IP_PU(IRQbank, IRQ)
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#define IRQ_IP_FL() CTL_IP_FL(IRQbank, IRQ)
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#define IRQ_OP() CTL_OP(IRQbank, IRQ)
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#define IRQ_LO() CTL_SET_LO(IRQbank, IRQ)
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#define IRQ_HI() CTL_SET_HI(IRQbank, IRQ)
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#define IRQ_RD(val) CTL_RD(IRQbank, IRQ, val)
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// PC11 "CIA10"
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#define CIA10_IP_PU() CTL_IP_PU(CIA10bank, CIA10)
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#define CIA10_IP_FL() CTL_IP_FL(CIA10bank, CIA10)
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#define CIA10_OP() CTL_OP(CIA10bank, CIA10)
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#define CIA10_LO() CTL_SET_LO(CIA10bank, CIA10)
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#define CIA10_HI() CTL_SET_HI(CIA10bank, CIA10)
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#define CIA10_RD(val) CTL_RD(CIA10bank, CIA10, val)
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// PC12 "BL"
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// PC13 "AXL"
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#ifndef C13nodef
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#ifdef PURPLE_KAZZO //tie two pins together via software
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#define AXL_IP_PU() CTL_IP_PU(AXLbank, AXL) CTL_IP_PU(FREEbank, FREE)
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#define AXL_IP_FL() CTL_IP_FL(AXLbank, AXL) CTL_IP_FL(FREEbank, FREE)
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#define AXL_OP() CTL_OP(AXLbank, AXL) CTL_OP(FREEbank, FREE)
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#define AXL_LO() CTL_SET_LO(AXLbank, AXL) CTL_SET_LO(FREEbank, FREE)
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#define AXL_HI() CTL_SET_HI(AXLbank, AXL) CTL_SET_HI(FREEbank, FREE)
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#define AXL_RD(val) CTL_RD(AXLbank, AXL, val)
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#else //not PURPLE_KAZZO
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#define AXL_IP_PU() CTL_IP_PU(AXLbank, AXL)
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#define AXL_IP_FL() CTL_IP_FL(AXLbank, AXL)
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#define AXL_OP() CTL_OP(AXLbank, AXL)
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#define AXL_LO() CTL_SET_LO(AXLbank, AXL)
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#define AXL_HI() CTL_SET_HI(AXLbank, AXL)
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#define AXL_RD(val) CTL_RD(AXLbank, AXL, val)
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#endif
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#endif
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// PC14 "AUDL"
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// PC15 "AUDR"
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// PC16 "GBP"
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#ifndef C16nodef
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#define GBP_IP_PU() CTL_IP_PU(GBPbank, GBP)
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#define GBP_IP_FL() CTL_IP_FL(GBPbank, GBP)
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#define GBP_OP() CTL_OP(GBPbank, GBP)
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#define GBP_LO() CTL_SET_LO(GBPbank, GBP)
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#define GBP_HI() CTL_SET_HI(GBPbank, GBP)
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#define GBP_3V() GBP_HI()
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#define GBP_5V() GBP_LO()
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#define GBP_RD(val) CTL_RD(GBPbank, GBP, val)
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#endif
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// PC17 "SWD"
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// PC18 "SWC"
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// PC19 "AFL"
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#ifndef C19nodef
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#define AFL_IP_PU() CTL_IP_PU(AFLbank, AFL)
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#define AFL_IP_FL() CTL_IP_FL(AFLbank, AFL)
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#define AFL_OP() CTL_OP(AFLbank, AFL)
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#define AFL_LO() CTL_SET_LO(AFLbank, AFL)
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#define AFL_HI() CTL_SET_HI(AFLbank, AFL)
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#define AFL_RD(val) CTL_RD(AFLbank, AFL, val)
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#endif
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// PC20 "COUT"
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// PC21 "FCAPU"
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////////////////////////////////
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// EXTRA (EXT) PORT PINS
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////////////////////////////////
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// PE0 "A0"
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#define A0_IP_PU() EXT_IP_PU(A0bank, A0)
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#define A0_IP_FL() EXT_IP_FL(A0bank, A0)
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#define A0_OP() EXT_OP(A0bank, A0)
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#define A0_LO() EXT_SET_LO(A0bank, A0)
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#define A0_HI() EXT_SET_HI(A0bank, A0)
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#define A0_RD(val) EXT_RD(A0bank, A0, val)
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#ifdef STM_CORE
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#define A0_OD() EXT_OD(A0bank, A0)
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#define A0_PP() EXT_PP(A0bank, A0)
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#endif
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// PE1 "D0"
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#define D0_IP_PU() EXT_IP_PU(D0bank, D0)
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#define D0_IP_FL() EXT_IP_FL(D0bank, D0)
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#define D0_OP() EXT_OP(D0bank, D0)
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#define D0_LO() EXT_SET_LO(D0bank, D0)
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#define D0_HI() EXT_SET_HI(D0bank, D0)
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#define D0_RD(val) EXT_RD(D0bank, D0, val)
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#ifdef STM_CORE
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#define D0_OD() EXT_OD(D0bank, D0)
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#define D0_PP() EXT_PP(D0bank, D0)
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#endif
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#endif //end of file
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