438 lines
16 KiB
C
438 lines
16 KiB
C
#ifndef _shared_dict_pinport_h
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#define _shared_dict_pinport_h
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//define dictionary's reference number in the shared_dictionaries.h file
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//then include this dictionary file in shared_dictionaries.h
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//The dictionary number is literally used as usb transfer request field
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//the opcodes and operands in this dictionary are fed directly into usb setup packet's wValue wIndex fields
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//=============================================================================================
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//=============================================================================================
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// PINPORT DICTIONARY
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//=============================================================================================
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//=============================================================================================
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//This file was created based on firmware version of pinport.h and pinport.c
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//the close relationship between these two files must be kept in mind when making changes.
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//This file is also very dependent on macro definitions in firmware.
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//Any changes to this file must be applied to firmware.
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//Don't recommend changing opcodes or anything here, change them in fw first then apply here.
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//making this a shared file helps cut room for error as changing opcode numbers here will
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//inherently get forwarded to both firmware and app at same time.
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//=============================================================================================
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// OPCODES with no operand and no return value besides SUCCESS/ERROR_CODE
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//=============================================================================================
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// 0x00-0x7F
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// 0-90: currently defined
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// 19-22: unused due to accidentaly double defining CICE opcodes
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// 91-127: not yet in use
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//
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// Current limit for these types of opcodes is 0-127
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// This allows for the MSB to be used for decoding pinport opcode to this type
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//
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// Detect this opcode/operand setup with opcode between the following defines:
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#define PP_OPCODE_ONLY_MIN 0x00
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#define PP_OPCODE_ONLY_MAX 0x7F
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//
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//=============================================================================================
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//=============================================================================================
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//============================
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//ADDR[7:0] PORTA
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//============================
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//DDR-PORT MACROS
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#define ADDR_IP 0
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#define ADDR_OP 1
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#define ADDR_LO 2
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#define ADDR_HI 3
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//============================
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//DATA[7:0] PORTB
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//============================
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//DDR-PORT MACROS
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#define DATA_IP 4
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#define DATA_OP 5
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#define DATA_LO 6
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#define DATA_HI 7
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//============================
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//CTL PORTC
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//============================
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//DDR-PORT MACROS
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#define CTL_IP 8
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// No CTL_OP() macro as some of these are inputs or bidir, best to individually assert as output
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#define CTL_LO 9
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#define CTL_HI 10
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//PIN MACROS
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#define M2_IP 11
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#define M2_OP 12
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#define M2_LO 13
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#define M2_HI 14
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#define ROMSEL_IP 15
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#define ROMSEL_OP 16
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#define ROMSEL_LO 17
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#define ROMSEL_HI 18
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#define PRGRW_IP 23
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#define PRGRW_OP 24
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#define PRGRW_WR 25 //LO for writes
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#define PRGRW_RD 26 //HI for reads
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//give each def different version numbers to detect errors
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//where command given to board which doesn't have that function
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//#ifdef PURPLE_KAZZO //purple boards only
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#define p_AXL_ip 27 //Don't use these, use software tied together versions instead.
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#define p_AXL_op 28 //Increases compatibility between versions
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#define p_AXL_lo 29 //Don't recommend calling lo/hi, use CLK instead
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#define p_AXL_hi 30
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//#else //Green and final design
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#define FREE_IP 31
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#define FREE_OP 32
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#define FREE_LO 33
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#define FREE_HI 34
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//#endif
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#define CSRD_IP 35
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#define CSRD_OP 36
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#define CSRD_LO 37
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#define CSRD_HI 38
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#define CSWR_IP 39
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#define CSWR_OP 40
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#define CSWR_LO 41
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#define CSWR_HI 42
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#define CICE_IP 43
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#define CICE_OP 44
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#define CICE_LO 45
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#define CICE_HI 46
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//#ifdef GREEN_KAZZO
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#define g_AXHL_IP 47
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#define g_AXHL_OP 48
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#define g_AXHL_lo 49 //Don't recommend calling these as AXHL should be left low
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#define g_AXHL_hi 50 //That way AXHL_CLK(); is always effective
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//#endif
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//purple and final design, safe to pretend green is similar due to software AHL/AXL CLK
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#define AHL_IP 51
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#define AHL_OP 52
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#define AHL_lo 53 //Don't recommend calling these as AHL should be left low
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#define AHL_hi 54 //That way AHL_CLK(); is always effective.
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//also helps maintain validity of software AHL/AXL CLK
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//============================
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//AUX PORTD
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//============================
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//DDR-PORT MACROS
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#define AUX_IP 55 //Don't touch USB pins!!!
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// No AUX_OP(); macro as many of these are inputs or bidir, best to individually assert as output
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#define AUX_LO 56
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#define AUX_HI 57
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//PIN MACROS
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//lower case aren't meant to be called unless certain pin is 5v tolerant
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#define EXP0_ip 58
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#define EXP0_op 59
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#define EXP0_lo 60 //Don't call this assuming EXP0 DDR is set to o/p
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#define EXP0_hi 61 //Don't call this unless you're certain pin is 5v tolerant
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//SNES versions uppercase as assuming 5v tolerance without NES cart
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#define SRST_IP 58
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#define SRST_OP 59
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#define SRST_LO 60
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#define SRST_HI 61
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//User options pull up, force low, and float
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#define EXP0_LO 62 //Sets low then DDR to o/p
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#define EXP0_PU 63 //maybe add some NOP(); to allow time for pull up
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#define EXP0_FLT 64 //Set to i/p w/o pullup
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#define LED_IP 65
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#define LED_OP 66
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#define LED_OFF 67
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#define LED_ON 68
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#define IRQ_IP 69
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#define IRQ_OP 70
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#define IRQ_LO 71
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#define IRQ_HI 72
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#define CIA10_IP 73
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#define CIA10_OP 74
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#define CIA10_LO 75
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#define CIA10_HI 76
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#define BL_IP 77
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#define BL_OP 78
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#define BL_LO 79
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#define BL_HI 80
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//#ifndef pg_XOE //FINAL_DESIGN
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//purple and green have versions of these which tie two pins together in software
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#define AXLOE_IP 81
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#define AXLOE_OP 82
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//Caution AXL_CLK() relies on EXPFF_OP() to be called beforehand
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// Think of it like you must enable the output before you can clock it.
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// Floating EXPFF also happens to clock it. Think of it like it looses it's value if disabled.
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//#ifdef PURPLE_KAZZO or GREEN_KAZZO //purple and green versions
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#define XOE_ip 83 //Don't call these, use AXLOE instead
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#define XOE_op 84
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#define XOE_lo 85
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#define XOE_hi 86
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//#endif
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//Same definition on all board versions
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//Only need to be cognizant that AXL_CLK won't work if EXPFF_FLT was called beforehand
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//This is only an issue on final design, so an error here should only cause probs on final design
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//Net effect is it it works on final design should be fine on other versions which is the goal
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#define EXPFF_OP 87 //FF /OE pin low->enable o/p
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#define EXPFF_FLT 88 //FF /OE pin high->disable o/p
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//AXL_CLK this is similar between purple and green versions, just on a different pin.
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//green boards don't have an AXL_CLK nor a AHL_CLK, as the two are combined.
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//green boards must resolve this in software storing value of FF's so can have the effect
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//of only clocking one of them.
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//#ifdef GREEN_KAZZO
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//case XX: AXHL_CLK(); break; //don't want to call this as software AXL/AHL don't track
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//case 87: software_AXL_CLK(); break;
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//case 88: software_AHL_CLK(); break;
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//#else
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//these two cases covers all designs with macro calling sofware versions for green board.
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#define AXL_CLK 89
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#define AHL_CLK 90
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//#endif
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//these work fine in hardware for purple and final.
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//green had to separate these two with software.
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//=============================================================================================
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//=============================================================================================
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// CAUTION!!! CAUTION!!! CAUTION!!! CAUTION!!! CAUTION!!!
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//
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// The opcodes that follow operate under some rules that you must adhere to if calling
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// 1) Data bus should be free and clear when possible
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// -DATA_IP() is default state
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// -Be cognizant if you're driving the data bus
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// many of these opcodes use the data bus to function.
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// -Many of these opcodes will end up driving the data bus
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// know when that'll happen and free bus when data retreived
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//
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// -Flipflops must be initialized
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// this primarily means CLK pin must be OP and LO ready for CLK command
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// -output of FF must be enabled to actually feed latched value on cart
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// final pcb version will enable EXP FF after clocking.
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// early pcb versions have FF /OE on separate pin not so automatic.
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//
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// -control pins must be initialized
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// -enable OP on pins necessary to perform desire of command
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// ie M2 and /ROMSEL must be OP if you're trying to change them with a command.
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//
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// -be cognizant of what pins are inputs and which are outputs
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// ie driving PPU /A13 will be fed back to CIRAM /CE so it needs to be IP
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// -if in doubt, leave it as input with pull up, atleast that shouldn't break anything
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//
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// -ADDR_OP is default state, these opcodes assume it to be set as it shouldn't conflict
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// -/ROMSEL & M2 expected to be set as outputs
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//
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//
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//=============================================================================================
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//=============================================================================================
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//=============================================================================================
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// OPCODES WITH OPERAND and no return value besides SUCCESS/ERROR_CODE
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//=============================================================================================
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//
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#define PP_OPCODE_8BOP_MIN 0x80
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#define PP_OPCODE_8BOP_MAX 0x9F
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// 0x80-0x9F: opcodes with 8bit operand
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// 0x80-8A are only ones currently in use
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//
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#define PP_OPCODE_16BOP_MIN 0xA0
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#define PP_OPCODE_16BOP_MAX 0xAF
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// 0xA0-0xAF: opcodes with 16bit operand
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// 0xA0-A2 are only ones currently in use
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//
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#define PP_OPCODE_24BOP_MIN 0xB0
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#define PP_OPCODE_24BOP_MAX 0xBF
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// 0xB0-0xBF: opcodes with 24bit operand
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// 0xA0 is currently only one in use
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//
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// Current limit for these types of opcodes is 128-191 (0x80-0xBF)
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// This allows for the MSBs' to be used for decoding pinport opcode to this type
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//
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//
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//=============================================================================================
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//=============================================================================================
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//=================================
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//8bit operand
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//=================================
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//ADDR[7:0] PORTA
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#define ADDR_SET 0x80
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//DATA[7:0] PORTB
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#define DATA_SET 0x81
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//conveinent/safe yet slower function that sets ADDR as OP then sets value
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#define DATA_OPnSET 0x82
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//ADDR[15:8] FLIPFLOP
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//NES CPU: ADDRH[6:0] -> CPU A[14:8]
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// ADDRH[7] -> NC on CPU side
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//NES PPU: ADDRH[5:0] -> PPU A[13:8]
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// ADDRH[6] -> NC on PPU side
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// ADDRH[7] -> PPU /A13 (which drives CIRAM /CE on most carts "2-screen mirroring")
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//SNES: ADDRH[7:0] -> CPU A[15:8]
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#define ADDRH_SET 0x83
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//EXPANSION FLIPFLOP
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//NES: ADDRX[7:0] -> EXP PORT [8:1]
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//SNES: ADDRX[7:0] -> CPU A[23:16]
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#define ADDRX_SET 0x84
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//Set ADDR/DATA bus DDR registers with bit granularity
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// OP() IP() macros affect entire 8bit port's direction
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// Each pin can be controlled individually though
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// This could be useful for advanced feature that doesn't treat DATA/ADDR as byte wide port.
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#define ADDR_DDR_SET 0x85
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#define DATA_DDR_SET 0x86
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//Perhaps it will be useful to have this function on other ports as well
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//But probably wouldn't be very useful if standard carts are plugged in..
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//AUX port operations will shield USB pins from being affected
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//defined as lower case because you shouldn't call these unless you *Really* know what you're doing..
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#define ctl_ddr_set 0x87
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#define aux_ddr_set 0x88
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#define ctl_port_set 0x89
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#define aux_port_set 0x8A
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//=================================
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//16bit operand
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//=================================
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//ADDR[15:0] (ADDRH:ADDR)
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//Doesn't affect control signals
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//bits[13:0] are applied to NES CPU, NES PPU, and SNES address bus
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//bit[14] is only applied to CPU A14 on NES
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//bit[15] is only applied to PPU /A13 on NES
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//bit[15:14] are applied to SNES A[15:14]
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#define ADDR16_SET 0xA0
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//Set NES CPU ADDRESS BUS SET with /ROMSEL
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//bit 15 is decoded to enable /ROMSEL properly (aka PRG /CE)
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//bit15 is actually inverted then applied to /ROMSEL since /ROMSEL is low when NES CPU A15 is high
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//NOTE! This does NOT affect M2 (aka phi2), so carts using M2 to decode things like WRAM is dependent on last value of M2
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//This will also stop current value of PPU /A13 with bit15
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#define NCPU_ADDR_ROMSEL 0xA1
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//TODO consider opcode that preserves PPU /A13 instead of stomping it like the opcodes above.
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//Can't think of why this would be useful so ignoring for now
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//One reason might be to keep VRAM silent on a NES board with 4screen mirroring..
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// But should be able to do this with CHR /RD in same manner CHR-ROM is kept silent..
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//Set NES PPU ADDRESS BUS with /A13
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//PPU address bus is 14bits wide A[13:0] so operand bits [15:14] are ignored.
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//bit 13 is inverted and applied to PPU /A13
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//PPU control signals CHR /RD and CHR /WR are unaffected
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//Note: since PPU /A13 is tied to ADDRH[7] could perform this faster by using ADDR16_SET
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// but this opcode is convienent and ensures PPU /A13 is always inverse of PPU A13
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// This is important for NES carts with on board CHR-ROM and VRAM for 4screen mirroring.
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#define NPPU_ADDR_SET 0xA2
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//=================================
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//24bit operand
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//=================================
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//ADDR[23:0] (ADDRX:ADDRH:ADDR) SNES full address bus
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//Sets SNES 24 bit address but to value of 24bit operand
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//No control signals are modified
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#define ADDR24_SET 0xB0
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//=============================================================================================
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// OPCODES with NO OPERAND but have RETURN VALUE plus SUCCESS/ERROR_CODE
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//=============================================================================================
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//
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#define PP_OPCODE_8BRV_MIN 0xC0
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#define PP_OPCODE_8BRV_MAX 0xFF
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// 0xC0-0xFF: opcodes with 8bit return value (plus SuCCESS/ERROR)
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// 0xC0-CB are only ones currently in use
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//
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// 0x??-0xFF: larger return values perhaps?
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//
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//
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// Current limit for these types of opcodes is 192-255 (0xC0-0xFF)
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// This allows for the MSBs' to be used for decoding pinport opcode to this type
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// Detect this opcode/operand setup with opcode between the following defines:
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//
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// Detect this opcode/operand setup with opcode between the following defines:
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//
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//=============================================================================================
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//=============================================================================================
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//READ MCU I/O PORT INPUT 'PIN' REGISTERS
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//This is what's used to read bus after setting DDR register to input with IP() command/macro
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//Current value of PORT Determines if pullups are activated or not, pull up with HI() macro, and float with LO() macro
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//ADDR[7:0] PINA
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#define ADDR_RD 0xC0
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//DATA[7:0] PINB
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#define DATA_RD 0xC1
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//CTL PINC
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//Should set pin of interest to input with IP with macros prior to reading
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//you're still allowed to read value even if some/all pins are output though
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#define CTL_RD 0xC2
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//AUX PIND
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//Should set pin of interest to input with IP with macros prior to reading
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//you're still allowed to read value even if some/all pins are output though
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#define AUX_RD 0xC3
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//READ MCU I/O PORT OUTPUT 'PORT' REGISTERS
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//Gives means to see what pins are currently being driven (or pulled up) to.
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//ADDR[7:0] PORTA
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#define ADDR_PORT_RD 0xC4
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//DATA[7:0] PORTB
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#define DATA_PORT_RD 0xC5
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//CTL PORTC
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#define CTL_PORT_RD 0xC6
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//AUX PORTD
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#define AUX_PORT_RD 0xC7
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//READ MCU I/O PORT DIRECTION 'DDR' REGISTERS
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//Gives means to see what pins are currently set to I/P or O/P.
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//ADDR[7:0] DDRA
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#define ADDR_DDR_RD 0xC8
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//DATA[7:0] DDRB
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#define DATA_DDR_RD 0xC9
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//CTL DDRC
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#define CTL_DDR_RD 0xCA
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//AUX DDRD
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#define AUX_DDR_RD 0xCB
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//=============================================================================================
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// OPCODES with OPERAND and RETURN VALUE plus SUCCESS/ERROR_CODE
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//=============================================================================================
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//Not sure if want these or not...
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#endif
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