484 lines
14 KiB
C
484 lines
14 KiB
C
#include "pinport.h"
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//This file was created based on pinport.h
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//the close relationship between these two files must be kept in mind when making changes.
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//This file is also very dependent on shared_dict_pinport.h
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//the shared_dict_pinport.h was generated from this file, so any changes here must be forwarded.
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/* Desc:Decode pinport dictionary calls transmitted via USB and call requested operation
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* shared_dict_pinport.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_dict_pinport.h
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* Post:opcode command complete, return data & length stored if used.
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* Rtn: SUCCESS if opcode found and completed, error code if not.
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*/
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uint8_t pinport_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata )
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{
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#define RD_LEN 0
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#define RD0 1
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#define RD1 2
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#define BYTE_LEN 1
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#define HWORD_LEN 2
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//create pointer to first two bytes of return data array
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uint16_t *ret_hword = (uint16_t*) &rdata[RD0];
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switch (opcode) {
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//============================
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//CONTROL PORT INDIVIDUAL PIN ACCESS
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//opcode: type of pin operation
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//operand: pin number to act on
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//============================
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case CTL_ENABLE_: CTL_ENABLE(); break;
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case CTL_IP_PU_:
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switch ( operand ) {
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case 0: CTL_IP_PU(C0bank, C0); break;
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case 1: CTL_IP_PU(C1bank, C1); break;
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case 2: CTL_IP_PU(C2bank, C2); break;
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#ifndef C3nodef
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case 3: CTL_IP_PU(C3bank, C3); break;
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#endif
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case 4: CTL_IP_PU(C4bank, C4); break;
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case 5: CTL_IP_PU(C5bank, C5); break;
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case 6: CTL_IP_PU(C6bank, C6); break;
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#ifndef C7nodef
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case 7: CTL_IP_PU(C7bank, C7); break;
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#endif
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case 8: CTL_IP_PU(C8bank, C8); break;
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case 9: CTL_IP_PU(C9bank, C9); break;
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case 10: CTL_IP_PU(C10bank,C10); break;
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case 11: CTL_IP_PU(C11bank,C11); break;
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#ifndef C12nodef
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case 12: CTL_IP_PU(C12bank,C12); break;
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#endif
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#ifndef C13nodef
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case 13: CTL_IP_PU(C13bank,C13);
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#ifdef PURPLE_KAZZO
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CTL_IP_PU(C3bank,C3);
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#endif
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break;
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#endif
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#ifndef C14nodef
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case 14: CTL_IP_PU(C14bank,C14); break;
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#endif
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#ifndef C15nodef
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case 15: CTL_IP_PU(C15bank,C15); break;
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#endif
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#ifndef C16nodef
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case 16: CTL_IP_PU(C16bank,C16); break;
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#endif
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#ifndef C17nodef
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case 17: CTL_IP_PU(C17bank,C17); break;
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#endif
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#ifndef C18nodef
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case 18: CTL_IP_PU(C18bank,C18); break;
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#endif
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#ifndef C19nodef
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case 19: CTL_IP_PU(C19bank,C19); break;
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#endif
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#ifndef C20nodef
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case 20: CTL_IP_PU(C20bank,C20); break;
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#endif
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case 21: CTL_IP_PU(C21bank,C21); break;
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default: return ERR_CTL_PIN_NOT_PRESENT;
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}
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break;
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case CTL_IP_FL_:
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switch ( operand ) {
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case 0: CTL_IP_FL(C0bank, C0); break;
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case 1: CTL_IP_FL(C1bank, C1); break;
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case 2: CTL_IP_FL(C2bank, C2); break;
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#ifndef C3nodef
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case 3: CTL_IP_FL(C3bank, C3); break;
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#endif
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case 4: CTL_IP_FL(C4bank, C4); break;
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case 5: CTL_IP_FL(C5bank, C5); break;
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case 6: CTL_IP_FL(C6bank, C6); break;
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#ifndef C7nodef
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case 7: CTL_IP_FL(C7bank, C7); break;
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#endif
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case 8: CTL_IP_FL(C8bank, C8); break;
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case 9: CTL_IP_FL(C9bank, C9); break;
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case 10: CTL_IP_FL(C10bank,C10); break;
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case 11: CTL_IP_FL(C11bank,C11); break;
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#ifndef C12nodef
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case 12: CTL_IP_FL(C12bank,C12); break;
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#endif
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#ifndef C13nodef
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case 13: CTL_IP_FL(C13bank,C13);
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#ifdef PURPLE_KAZZO
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CTL_IP_FL(C3bank,C3);
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#endif
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break;
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#endif
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#ifndef C14nodef
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case 14: CTL_IP_FL(C14bank,C14); break;
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#endif
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#ifndef C15nodef
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case 15: CTL_IP_FL(C15bank,C15); break;
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#endif
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#ifndef C16nodef
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case 16: CTL_IP_FL(C16bank,C16); break;
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#endif
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#ifndef C17nodef
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case 17: CTL_IP_FL(C17bank,C17); break;
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#endif
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#ifndef C18nodef
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case 18: CTL_IP_FL(C18bank,C18); break;
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#endif
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#ifndef C19nodef
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case 19: CTL_IP_FL(C19bank,C19); break;
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#endif
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#ifndef C20nodef
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case 20: CTL_IP_FL(C20bank,C20); break;
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#endif
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case 21: CTL_IP_FL(C21bank,C21); break;
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default: return ERR_CTL_PIN_NOT_PRESENT;
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}
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break;
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case CTL_OP_:
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switch ( operand ) {
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case 0: CTL_OP(C0bank, C0); break;
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case 1: CTL_OP(C1bank, C1); break;
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case 2: CTL_OP(C2bank, C2); break;
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#ifndef C3nodef
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case 3: CTL_OP(C3bank, C3); break;
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#endif
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case 4: CTL_OP(C4bank, C4); break;
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case 5: CTL_OP(C5bank, C5); break;
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case 6: CTL_OP(C6bank, C6); break;
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#ifndef C7nodef
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case 7: CTL_OP(C7bank, C7); break;
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#endif
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case 8: CTL_OP(C8bank, C8); break;
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case 9: CTL_OP(C9bank, C9); break;
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case 10: CTL_OP(C10bank,C10); break;
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case 11: CTL_OP(C11bank,C11); break;
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#ifndef C12nodef
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case 12: CTL_OP(C12bank,C12); break;
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#endif
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#ifndef C13nodef
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case 13: CTL_OP(C13bank,C13);
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#ifdef PURPLE_KAZZO
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CTL_OP(C3bank,C3);
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#endif
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break;
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#endif
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#ifndef C14nodef
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case 14: CTL_OP(C14bank,C14); break;
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#endif
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#ifndef C15nodef
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case 15: CTL_OP(C15bank,C15); break;
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#endif
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#ifndef C16nodef
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case 16: CTL_OP(C16bank,C16); break;
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#endif
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#ifndef C17nodef
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case 17: CTL_OP(C17bank,C17); break;
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#endif
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#ifndef C18nodef
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case 18: CTL_OP(C18bank,C18); break;
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#endif
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#ifndef C19nodef
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case 19: CTL_OP(C19bank,C19); break;
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#endif
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#ifndef C20nodef
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case 20: CTL_OP(C20bank,C20); break;
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#endif
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case 21: CTL_OP(C21bank,C21); break;
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default: return ERR_CTL_PIN_NOT_PRESENT;
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}
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break;
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case CTL_SET_LO_:
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switch ( operand ) {
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case 0: CTL_SET_LO(C0bank, C0); break;
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case 1: CTL_SET_LO(C1bank, C1); break;
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case 2: CTL_SET_LO(C2bank, C2); break;
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#ifndef C3nodef
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case 3: CTL_SET_LO(C3bank, C3); break;
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#endif
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case 4: CTL_SET_LO(C4bank, C4); break;
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case 5: CTL_SET_LO(C5bank, C5); break;
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case 6: CTL_SET_LO(C6bank, C6); break;
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#ifndef C7nodef
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case 7: CTL_SET_LO(C7bank, C7); break;
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#endif
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case 8: CTL_SET_LO(C8bank, C8); break;
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case 9: CTL_SET_LO(C9bank, C9); break;
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case 10: CTL_SET_LO(C10bank,C10); break;
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case 11: CTL_SET_LO(C11bank,C11); break;
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#ifndef C12nodef
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case 12: CTL_SET_LO(C12bank,C12); break;
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#endif
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#ifndef C13nodef
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case 13: CTL_SET_LO(C13bank,C13);
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#ifdef PURPLE_KAZZO
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CTL_SET_LO(C3bank,C3);
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#endif
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break;
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#endif
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#ifndef C14nodef
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case 14: CTL_SET_LO(C14bank,C14); break;
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#endif
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#ifndef C15nodef
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case 15: CTL_SET_LO(C15bank,C15); break;
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#endif
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#ifndef C16nodef
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case 16: CTL_SET_LO(C16bank,C16); break;
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#endif
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#ifndef C17nodef
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case 17: CTL_SET_LO(C17bank,C17); break;
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#endif
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#ifndef C18nodef
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case 18: CTL_SET_LO(C18bank,C18); break;
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#endif
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#ifndef C19nodef
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case 19: CTL_SET_LO(C19bank,C19); break;
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#endif
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#ifndef C20nodef
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case 20: CTL_SET_LO(C20bank,C20); break;
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#endif
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case 21: CTL_SET_LO(C21bank,C21); break;
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default: return ERR_CTL_PIN_NOT_PRESENT;
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}
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break;
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case CTL_SET_HI_:
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switch ( operand ) {
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case 0: CTL_SET_HI(C0bank, C0); break;
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case 1: CTL_SET_HI(C1bank, C1); break;
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case 2: CTL_SET_HI(C2bank, C2); break;
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#ifndef C3nodef
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case 3: CTL_SET_HI(C3bank, C3); break;
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#endif
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case 4: CTL_SET_HI(C4bank, C4); break;
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case 5: CTL_SET_HI(C5bank, C5); break;
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case 6: CTL_SET_HI(C6bank, C6); break;
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#ifndef C7nodef
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case 7: CTL_SET_HI(C7bank, C7); break;
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#endif
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case 8: CTL_SET_HI(C8bank, C8); break;
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case 9: CTL_SET_HI(C9bank, C9); break;
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case 10: CTL_SET_HI(C10bank,C10); break;
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case 11: CTL_SET_HI(C11bank,C11); break;
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#ifndef C12nodef
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case 12: CTL_SET_HI(C12bank,C12); break;
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#endif
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#ifndef C13nodef
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case 13: CTL_SET_HI(C13bank,C13);
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#ifdef PURPLE_KAZZO
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CTL_SET_HI(C3bank,C3);
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#endif
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break;
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#endif
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#ifndef C14nodef
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case 14: CTL_SET_HI(C14bank,C14); break;
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#endif
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#ifndef C15nodef
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case 15: CTL_SET_HI(C15bank,C15); break;
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#endif
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#ifndef C16nodef
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case 16: CTL_SET_HI(C16bank,C16); break;
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#endif
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#ifndef C17nodef
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case 17: CTL_SET_HI(C17bank,C17); break;
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#endif
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#ifndef C18nodef
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case 18: CTL_SET_HI(C18bank,C18); break;
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#endif
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#ifndef C19nodef
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case 19: CTL_SET_HI(C19bank,C19); break;
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#endif
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#ifndef C20nodef
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case 20: CTL_SET_HI(C20bank,C20); break;
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#endif
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case 21: CTL_SET_HI(C21bank,C21); break;
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default: return ERR_CTL_PIN_NOT_PRESENT;
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}
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break;
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case CTL_RD_:
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rdata[RD_LEN] = HWORD_LEN;
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switch ( operand ) {
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case 0: CTL_RD(C0bank, C0, *ret_hword); break;
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case 1: CTL_RD(C1bank, C1, *ret_hword); break;
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case 2: CTL_RD(C2bank, C2, *ret_hword); break;
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#ifndef C3nodef
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case 3: CTL_RD(C3bank, C3, *ret_hword); break;
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#endif
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case 4: CTL_RD(C4bank, C4, *ret_hword); break;
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case 5: CTL_RD(C5bank, C5, *ret_hword); break;
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case 6: CTL_RD(C6bank, C6, *ret_hword); break;
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#ifndef C7nodef
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case 7: CTL_RD(C7bank, C7, *ret_hword); break;
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#endif
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case 8: CTL_RD(C8bank, C8, *ret_hword); break;
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case 9: CTL_RD(C9bank, C9, *ret_hword); break;
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case 10: CTL_RD(C10bank,C10, *ret_hword); break;
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case 11: CTL_RD(C11bank,C11, *ret_hword); break;
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#ifndef C12nodef
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case 12: CTL_RD(C12bank,C12, *ret_hword); break;
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#endif
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#ifndef C13nodef
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case 13: CTL_RD(C13bank,C13, *ret_hword); break;
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#endif
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#ifndef C14nodef
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case 14: CTL_RD(C14bank,C14, *ret_hword); break;
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#endif
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#ifndef C15nodef
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case 15: CTL_RD(C15bank,C15, *ret_hword); break;
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#endif
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#ifndef C16nodef
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case 16: CTL_RD(C16bank,C16, *ret_hword); break;
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#endif
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#ifndef C17nodef
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case 17: CTL_RD(C17bank,C17, *ret_hword); break;
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#endif
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#ifndef C18nodef
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case 18: CTL_RD(C18bank,C18, *ret_hword); break;
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#endif
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#ifndef C19nodef
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case 19: CTL_RD(C19bank,C19, *ret_hword); break;
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#endif
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#ifndef C20nodef
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case 20: CTL_RD(C20bank,C20, *ret_hword); break;
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#endif
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case 21: CTL_RD(C21bank,C21, *ret_hword); break;
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default: rdata[RD_LEN] = 0;
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return ERR_CTL_PIN_NOT_PRESENT;
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}
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break;
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//============================
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//DATA PORT BYTE WIDE ACCESS
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//opcode: type of operation
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//operand: value to place on bus
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//============================
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case DATA_ENABLE_: DATA_ENABLE(); break;
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case DATA_IP_PU_: DATA_IP_PU(); break;
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case DATA_IP_: DATA_IP(); break;
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case DATA_OP_: DATA_OP(); break;
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case DATA_SET_: DATA_SET(operand); break;
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case DATA_RD_: DATA_RD(rdata[RD0]);
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rdata[RD_LEN] = 1; break;
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//============================
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//ADDR PORT 16bit WIDE ACCESS
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//opcode: type of operation
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//operand: value to place on bus
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//============================
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case ADDR_ENABLE_: ADDR_ENABLE(); break;
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case ADDR_PU_: ADDR_PU(); break;
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case ADDR_IP_: ADDR_IP(); break;
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case ADDR_OP_: ADDR_OP(); break;
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case ADDR_SET_: ADDR_SET(operand); break;
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//============================
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//EXP PORT 8bit ACCESS (bits1-8)
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//opcode: type of operation
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//operand: value to place on bus
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//============================
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case EXP_ENABLE_: EXP_ENABLE(); break;
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case EXP_DISABLE_: EXP_DISABLE(); break;
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case EXP_SET_: EXP_SET(operand); break;
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default:
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//macro doesn't exist or isn't on this PCB version
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return ERR_UNKN_PP_OPCODE;
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}
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return SUCCESS;
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}
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#ifdef GREEN_KAZZO
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/* Desc:
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* other board versions have PORTB "DATA" feed into both FF's
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* this board feeds EXP FF with PORTA "ADDR" instead
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* goal is to make board versions 'identical'
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* to do this we assume higher level functions will have already
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* placed desired latch value on PORTB "Dbank->PORT"
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* we need to juggle this data around and not stomp on anything
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* Pre: DATA_OP() set
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* curAHLaddr set by software_AHL_CLK
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* Dbank->PORT contains desired value to be latched by EXP FF
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* AXHL might not be set as O/P
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* AXHL might not be low ready for AXHL_CLK
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* Post:Both FF's have desired value latched
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* ADDR_OP() left set
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* curAXLaddr updated for use by software_AHL_CLK
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* Dbank->PORT and ALbank->PORT replaced with original values
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* AXHL left as O/P and ready for subsequent CLK
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*/
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//these variables are updated each time the FF's are clocked
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//that way we can retain the value of other FF as both must be clocked at once
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static uint8_t curAHLaddr;
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static uint8_t curAXLaddr;
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void software_AXL_CLK()
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{
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//first store current DATA & ADDR values
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curAXLaddr = Dbank->PORT; //This is desired AXL value
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uint8_t orig_addr = ALbank->PORT; //PORTA
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//Put current AHL latched value on DATA as that's where it'll be relatched
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//software_AHL_CLK function is one to maintain this value
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Dbank->PORT = curAHLaddr;
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//set ADDR as O/P and place desired value on bus
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ADDR_OP(); //prob already be set, but in case not
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ALbank->PORT = curAXLaddr;
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//Clock both latches
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AHL_OP(); //can't be sure "AHL" is OP as assumption is AXL will be used as latch
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AHL_LO(); //can't be sure it's low either
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//_AXHL_CLK(); //clock values
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CTL_SET_HI(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL);
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//finally restore original DATA & ADDR values
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Dbank->PORT = curAXLaddr;
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ALbank->PORT = orig_addr;
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}
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/* Desc: Same premise as software_AXL_CLK above.
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* this is a little simpler as data has already been feed with AHL value.
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* just need to make sure AXL latch doesn't get corrupted.
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* Pre: DATA_OP() set
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* curAXLaddr set by software_AXL_CLK
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* Dbank->PORT contains desired value to be latched by ADDRMID FF
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* AXHL is already set to O/P
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* AXHL already low ready for AXHL_CLK
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* Post:Both FF's have desired value latched
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* curAHLaddr updated for use by software_AXL_CLK
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* Dbank->PORT and ALbank->PORT replaced with original values
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* AXHL left as O/P and ready for subsequent CLK
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*/
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void software_AHL_CLK()
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{
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//first store current DATA & ADDR values
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curAHLaddr = Dbank->PORT; //This is desired AHL value (store it for other function's use)
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uint8_t orig_addr = ALbank->PORT; //PORTA
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//Desired AHL latch value should have already been placed on Dbank->PORT.
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//set ADDR as O/P and place curAXLaddr on bus other function should have updated it last latch
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ADDR_OP(); //should already be set, but in case not
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ALbank->PORT = curAXLaddr;
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//Clock both latches
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//Can assume AHL is OP as other versions would require it to latch AHL
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//Can also assume it was left low, if not causes issues in all board versions
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//_AXHL_CLK(); //clock values
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CTL_SET_HI(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL);
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//finally restore original DATA & ADDR values
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//never changed: Dbank->PORT = curAHLaddr;
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ALbank->PORT = orig_addr;
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}
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#endif //GREEN_KAZZO
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