801 lines
19 KiB
C
801 lines
19 KiB
C
#include "nes.h"
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//=================================================================================================
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//
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// NES operations
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// This file includes all the nes functions possible to be called from the nes dictionary.
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//
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// See description of the commands contained here in shared/shared_dictionaries.h
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//
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//=================================================================================================
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/* Desc:Function takes an opcode which was transmitted via USB
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* then decodes it to call designated function.
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* shared_dict_nes.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_dict_nes.h
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* Post:function call complete.
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* Rtn: SUCCESS if opcode found and completed, error if opcode not present or other problem.
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*/
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uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata )
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{
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#define RD_LEN 0
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#define RD0 1
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#define RD1 2
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#define BYTE_LEN 1
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#define HWORD_LEN 2
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switch (opcode) {
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// //no return value:
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case DISCRETE_EXP0_PRGROM_WR:
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discrete_exp0_prgrom_wr( operand, miscdata );
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break;
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case DISC_PUSH_EXP0_PRGROM_WR:
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disc_push_exp0_prgrom_wr( operand, miscdata );
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break;
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case NES_PPU_WR:
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nes_ppu_wr( operand, miscdata );
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break;
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case NES_CPU_WR:
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nes_cpu_wr( operand, miscdata );
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break;
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case NES_DUALPORT_WR:
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nes_dualport_wr( operand, miscdata );
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break;
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// case DISCRETE_EXP0_MAPPER_WR:
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// discrete_exp0_mapper_wr( operand, miscdata );
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// break;
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case NES_MMC1_WR:
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mmc1_wr( operand, miscdata, 0 );
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break;
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//8bit return values:
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case EMULATE_NES_CPU_RD:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = emulate_nes_cpu_rd( operand );
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break;
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case NES_CPU_RD:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = nes_cpu_rd( operand );
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break;
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case NES_PPU_RD:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = nes_ppu_rd( operand );
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break;
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case NES_DUALPORT_RD:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = nes_dualport_rd( operand );
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break;
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case CIRAM_A10_MIRROR:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = ciram_a10_mirroring( );
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break;
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default:
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//macro doesn't exist
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return ERR_UNKN_NES_OPCODE;
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}
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return SUCCESS;
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}
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/* Desc: Discrete board PRG-ROM only write, does not write to mapper
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* PRG-ROM /WE <- EXP0 w/PU
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* PRG-ROM /OE <- /ROMSEL
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* PRG-ROM /CE <- GND
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* PRG-ROM write: /WE & /CE low, /OE high
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* mapper '161 CLK <- /ROMSEL
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* mapper '161 /LOAD <- PRG R/W
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* mapper '161 /LOAD must be low on rising edge of CLK to latch data
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* This is a /WE controlled write. Address latched on falling edge,
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* and data latched on rising edge EXP0
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* Note:addrH bit7 has no effect (ends up on PPU /A13)
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* /ROMSEL, M2, & PRG R/W signals untouched
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* Pre: nes_init() setup of io pins
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* Post:data latched by PRG-ROM, mapper register unaffected
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* address left on bus
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* data left on bus, but pullup only
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* EXP0 left pulled up
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* Rtn: None
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*/
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void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
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{
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ADDR_SET(addr);
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DATA_OP();
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DATA_SET(data);
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EXP0_OP(); //Tas = 0ns, Tah = 30ns
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EXP0_LO();
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EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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//16Mhz avr clk = 62.5ns period guarantees timing reqts
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DATA_IP();
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}
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//like above, but push on EXP0 instead of pullup
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void disc_push_exp0_prgrom_wr( uint16_t addr, uint8_t data )
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{
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ADDR_SET(addr);
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DATA_OP();
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DATA_SET(data);
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EXP0_OP(); //Tas = 0ns, Tah = 30ns
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EXP0_LO();
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//EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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EXP0_HI(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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//16Mhz avr clk = 62.5ns period guarantees timing reqts
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DATA_IP();
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}
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/* Desc: Discrete board MAPPER write without bus conflicts
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* will also write to PRG-ROM, but PRG-ROM shouldn't output
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* data while writting to mapper. Thus removing need for bank table.
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* NOTE: I think it would be possible to write one value to mapper
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* and another value to PRG-ROM.
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* PRG-ROM /WE <- EXP0 w/PU
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* PRG-ROM /OE <- /ROMSEL
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* PRG-ROM /CE <- GND
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* PRG-ROM write: /WE & /CE low, /OE high
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* mapper '161 CLK <- /ROMSEL
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* mapper '161 /LOAD <- PRG R/W
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* mapper '161 /LOAD must be low on rising edge of CLK to latch data
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* Note:addrH bit7 has no effect (ends up on PPU /A13)
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* M2 signal untouched
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* Pre: nes_init() setup of io pins
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* Post:data latched by MAPPER, will also be written to PRG-ROM afterwards
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* address left on bus
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* data left on bus, but pullup only
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* EXP0 left pulled up
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* Rtn: None
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*/
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//void discrete_exp0_mapper_wr( uint16_t addr, uint8_t data )
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//{
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// //Float EXP0 as it should be in NES
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// EXP0_IP_FL();
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// //EXP0_OP(); //tas = 0ns, tah = 30ns
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// //EXP0_LO();
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//
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// //need for whole function
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// //_DATA_OP();
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//
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// //set addrL
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// //ADDR_OUT = addrL;
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// //latch addrH
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// //DATA_OUT = addrH;
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// //_AHL_CLK();
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// ADDR_SET(addr);
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//
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// //PRG R/W LO
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// PRGRW_LO();
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//
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// //put data on bus
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// DATA_OP();
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// DATA_SET(data);
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//
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// //set M2 and /ROMSEL
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// M2_HI();
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// if( addr >= 0x8000 ) { //addressing cart rom space
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// ROMSEL_LO(); //romsel trails M2 during CPU operations
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// }
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//
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// //give some time
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// NOP();
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// NOP();
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//
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// //latch data to cart memory/mapper
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// M2_LO();
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// ROMSEL_HI();
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//
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// //retore PRG R/W to default
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// PRGRW_HI();
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//
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// EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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// //Free data bus
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// DATA_IP();
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//
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// return;
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//
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// /*
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// ADDR_SET(addr);
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//
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// DATA_OP();
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// DATA_SET(data);
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//
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// //start write to PRG-ROM (latch address)
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// exp0_op(); //tas = 0ns, tah = 30ns
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// exp0_lo();
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//
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// //enable write to mapper PRG R/W LO
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// PRGRW_LO();
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// ROMSEL_LO(); //fact that it's low for such a short time might also if PRG-ROM does output data
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//
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// //clock mapper register, should not enable PRG-ROM output since /WE low
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// ROMSEL_HI(); //data latched on rising edge
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//
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// //Could output other data here that would like to be written to PRG-ROM
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// //I'm not certain an actual write gets applied to PRG-ROM as /OE is supposed to be high whole time..
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//
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// NOP(); //AVR didn't need this delay
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// //return to default
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// PRGRW_HI();
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//
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// EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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// //16Mhz avr clk = 62.5ns period guarantees timing reqts
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// DATA_IP();
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// */
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//}
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/* Desc:Emulate NES CPU Read as best possible
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* decode A15 from addrH to set /ROMSEL as expected
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* float EXP0
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* toggle M2 as NES would
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* insert some NOP's in to be slow like NES
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* Note:not the fastest read operation
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* data bus left clear
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* EXP0 left floating
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* Rtn: Byte read from PRG-ROM at addrHL
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*/
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uint8_t emulate_nes_cpu_rd( uint16_t addr )
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{
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uint8_t read; //return value
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//m2 should be low as it aids in disabling WRAM
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//this is also m2 state at beginging of CPU cycle
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//all these pins should already be in this state, but
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//go ahead and setup just to be sure since we're trying
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//to be as accurate as possible
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EXP0_IP_FL(); //this could have been left pulled up
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M2_LO(); //start of CPU cycle
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ROMSEL_HI(); //trails M2
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PRGRW_HI(); //happens just after M2
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//set address bus
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ADDR_SET(addr);
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//couple NOP's to wait a bit
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NOP();
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NOP();
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//set M2 and /ROMSEL
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if( addr >= 0x8000 ) { //addressing cart rom space
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M2_HI();
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ROMSEL_LO(); //romsel trails M2 during CPU operations
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} else {
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M2_HI();
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}
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//couple more NOP's waiting for data
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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//latch data
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DATA_RD(read);
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//return bus to default
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M2_LO();
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ROMSEL_HI();
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return read;
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}
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/* Desc:NES CPU Read without being so slow
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* decode A15 from addrH to set /ROMSEL as expected
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* float EXP0
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* toggle M2 as NES would
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* data bus left clear
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* EXP0 left floating
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* Rtn: Byte read from PRG-ROM at addrHL
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*/
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uint8_t nes_cpu_rd( uint16_t addr )
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{
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uint8_t read; //return value
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//set address bus
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ADDR_SET(addr);
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//set M2 and /ROMSEL
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M2_HI();
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if( addr >= 0x8000 ) { //addressing cart rom space
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ROMSEL_LO(); //romsel trails M2 during CPU operations
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}
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//couple more NOP's waiting for data
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//zero nop's returned previous databus value
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NOP(); //one nop got most of the bits right
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NOP(); //two nop got all the bits right
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NOP(); //add third nop for some extra
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NOP(); //one more can't hurt
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//might need to wait longer for some carts...
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//latch data
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DATA_RD(read);
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//return bus to default
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M2_LO();
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ROMSEL_HI();
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return read;
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}
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/* Desc:NES CPU Write
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* Just as you would expect NES's CPU to perform
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* A15 decoded to enable /ROMSEL
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* This ends up as a M2 and/or /ROMSEL controlled write
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* Note:addrH bit7 has no effect (ends up on PPU /A13)
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* EXP0 floating
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* Pre: nes_init() setup of io pins
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* Post:data latched by anything listening on the bus
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* address left on bus
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* data left on bus, but pullup only
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* Rtn: None
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*/
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void nes_cpu_wr( uint16_t addr, uint8_t data )
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{
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//Float EXP0 as it should be in NES
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EXP0_IP_FL();
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//need for whole function
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//_DATA_OP();
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//set addrL
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//ADDR_OUT = addrL;
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//latch addrH
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//DATA_OUT = addrH;
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//_AHL_CLK();
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ADDR_SET(addr);
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//PRG R/W LO
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PRGRW_LO();
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//put data on bus
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DATA_OP();
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DATA_SET(data);
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//set M2 and /ROMSEL
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M2_HI();
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if( addr >= 0x8000 ) { //addressing cart rom space
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ROMSEL_LO(); //romsel trails M2 during CPU operations
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}
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//give some time
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NOP();
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NOP();
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//latch data to cart memory/mapper
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M2_LO();
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ROMSEL_HI();
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//retore PRG R/W to default
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PRGRW_HI();
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//Free data bus
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DATA_IP();
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}
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/* Desc:NES PPU Read
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* decode A13 from addrH to set /A13 as expected
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* data bus left clear
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* Rtn: Byte read from CHR-ROM/RAM at addrHL
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*/
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uint8_t nes_ppu_rd( uint16_t addr )
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{
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uint8_t read; //return value
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//addr with PPU /A13
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if (addr < 0x2000) { //below $2000 A13 clear, /A13 set
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addr |= PPU_A13N_WORD;
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} //above PPU $1FFF, A13 set, /A13 clear
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ADDR_SET( addr );
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//set CHR /RD and /WR
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CSRD_LO();
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//couple more NOP's waiting for data
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//zero nop's returned previous databus value
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NOP(); //one nop got most of the bits right
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NOP(); //two nop got all the bits right
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NOP(); //add third nop for some extra
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NOP(); //one more can't hurt
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//might need to wait longer for some carts...
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//latch data
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DATA_RD(read);
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//return bus to default
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CSRD_HI();
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return read;
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}
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/* Desc:NES PPU Write
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* decode A13 from addrH to set /A13 as expected
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* flash: address clocked falling edge, data rising edge of /WE
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* Pre: nes_init() setup of io pins
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* Post:data written to addrHL
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* address left on bus
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* data bus left clear
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* Rtn: None
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*/
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void nes_ppu_wr( uint16_t addr, uint8_t data )
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{
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//addr with PPU /A13
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if (addr < 0x2000) { //below $2000 A13 clear, /A13 set
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addr |= PPU_A13N_WORD;
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} //above PPU $1FFF, A13 set, /A13 clear
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ADDR_SET( addr );
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//put data on bus
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DATA_OP();
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DATA_SET(data);
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NOP();
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//set CHR /RD and /WR
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CSWR_LO();
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//might need to wait longer for some carts...
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NOP(); //one can't hurt
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//latch data to memory
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CSWR_HI();
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//clear data bus
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DATA_IP();
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}
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/* Desc:NES dual port Read from the PPU
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* /A13 as ignored
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* data bus left clear
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* Rtn: Byte read from CHR-ROM/RAM at addrHL
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*/
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uint8_t nes_dualport_rd( uint16_t addr )
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{
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uint8_t read; //return value
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ADDR_SET( addr );
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//enable data path
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M2_HI(); //M2 is kinda like R/W setting direction
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ROMSEL_LO(); //enable data buffers
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//data should now be driven on the bus but invalid
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//set CHR /RD and /WR
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CSRD_LO();
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//couple more NOP's waiting for data
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//zero nop's returned previous databus value
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NOP(); //one nop got most of the bits right
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NOP(); //two nop got all the bits right
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NOP(); //add third nop for some extra
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//latch data
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DATA_RD(read);
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//return bus to default
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CSRD_HI();
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M2_LO();
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ROMSEL_HI();
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return read;
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}
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/* Desc:NES DUALPORT Write
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* /A13 ignored
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* Pre: nes_init() setup of io pins
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* Post:data written to addrHL
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* address left on bus
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* data bus left clear
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* Rtn: None
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*/
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void nes_dualport_wr( uint16_t addr, uint8_t data )
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{
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ADDR_SET( addr );
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//enable data path
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M2_LO(); //M2 is kinda like R/W setting direction
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ROMSEL_LO(); //enable data buffers
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//data should now be driven on the bus but invalid
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//put data on bus
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DATA_OP();
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DATA_SET(data);
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NOP();
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//set CHR /RD and /WR
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|
CSWR_LO();
|
|
|
|
//might need to wait longer for some carts...
|
|
NOP(); //one can't hurt
|
|
|
|
//latch data to memory
|
|
CSWR_HI();
|
|
|
|
//clear data bus
|
|
DATA_IP();
|
|
ROMSEL_HI();
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Desc:PPU CIRAM A10 NT arrangement sense
|
|
* Toggle A11 and A10 and read back CIRAM A10
|
|
* report back if vert/horiz/1scnA/1scnB
|
|
* reports nesdev defined mirroring
|
|
* does not report Nintendo's "Name Table Arrangement"
|
|
* Pre: nes_init() setup of io pins
|
|
* Post:address left on bus
|
|
* Rtn: MIR_VERT, MIR_HORIZ, MIR_1SCNA, MIR_1SCNB
|
|
* errors not really possible since all combinations
|
|
* of CIRAM A10 level designate something valid
|
|
*/
|
|
uint8_t ciram_a10_mirroring( void )
|
|
{
|
|
uint16_t readV, readH;
|
|
|
|
//set A11, clear A10
|
|
//ADDRH(A11_BYTE); setting A11 in this manner doesn't work for some reason..
|
|
ADDR_SET(0x0800);
|
|
CIA10_RD(readH);
|
|
|
|
//set A10, clear A11
|
|
ADDRH(A10_BYTE);
|
|
//ADDR_SET(0x0400);
|
|
CIA10_RD(readV);
|
|
|
|
|
|
//if CIRAM A10 was always low -> 1 screen A
|
|
if ((readV==0) & (readH==0)) return MIR_1SCNA;
|
|
//if CIRAM A10 was always high -> 1 screen B
|
|
if ((readV!=0) & (readH!=0)) return MIR_1SCNB;
|
|
//if CIRAM A10 toggled with A10 -> Vertical mirroring, horizontal arrangement
|
|
if ((readV!=0) & (readH==0)) return MIR_VERT;
|
|
//if CIRAM A10 toggled with A11 -> Horizontal mirroring, vertical arrangement
|
|
if ((readV==0) & (readH!=0)) return MIR_HORZ;
|
|
|
|
//shouldn't be here...
|
|
return GEN_FAIL;
|
|
}
|
|
|
|
/* Desc:NES CPU Page Read with optional USB polling
|
|
* decode A15 from addrH to set /ROMSEL as expected
|
|
* float EXP0
|
|
* toggle M2 as NES would
|
|
* if poll is true calls usbdrv.h usbPoll fuction
|
|
* this is needed to keep from timing out when double buffering usb data
|
|
* Pre: nes_init() setup of io pins
|
|
* num_bytes can't exceed 256B page boundary
|
|
* Post:address left on bus
|
|
* data bus left clear
|
|
* EXP0 left floating
|
|
* data buffer filled starting at first to last
|
|
* Rtn: Index of last byte read
|
|
*/
|
|
uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
|
|
{
|
|
uint8_t i;
|
|
|
|
//set address bus
|
|
ADDRH(addrH);
|
|
|
|
//set M2 and /ROMSEL
|
|
M2_HI();
|
|
if( addrH >= 0x80 ) { //addressing cart rom space
|
|
ROMSEL_LO(); //romsel trails M2 during CPU operations
|
|
}
|
|
|
|
//set lower address bits
|
|
ADDRL(first); //doing this prior to entry and right after latching
|
|
//extra NOP was needed on stm6 as address hadn't settled in time for the very first read
|
|
NOP();
|
|
//gives longest delay between address out and latching data
|
|
for( i=0; i<=len; i++ ) {
|
|
//testing shows that having this if statement doesn't affect overall dumping speed
|
|
if ( poll == FALSE ) {
|
|
NOP(); //couple more NOP's waiting for data
|
|
NOP(); //one prob good enough considering the if/else
|
|
} else {
|
|
usbPoll(); //Call usbdrv.h usb polling while waiting for data
|
|
}
|
|
//latch data
|
|
DATA_RD(data[i]);
|
|
//set lower address bits
|
|
//ADDRL(++first); THIS broke things, on stm adapter because macro expands it twice!
|
|
first++;
|
|
ADDRL(first);
|
|
}
|
|
|
|
//return bus to default
|
|
M2_LO();
|
|
ROMSEL_HI();
|
|
|
|
//return index of last byte read
|
|
return i;
|
|
}
|
|
|
|
/* Desc:NES PPU Page Read with optional USB polling
|
|
* decode A13 from addrH to set /A13 as expected
|
|
* if poll is true calls usbdrv.h usbPoll fuction
|
|
* this is needed to keep from timing out when double buffering usb data
|
|
* Pre: nes_init() setup of io pins
|
|
* num_bytes can't exceed 256B page boundary
|
|
* Post:address left on bus
|
|
* data bus left clear
|
|
* data buffer filled starting at first for len number of bytes
|
|
* Rtn: Index of last byte read
|
|
*/
|
|
uint8_t nes_ppu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
|
|
{
|
|
uint8_t i;
|
|
|
|
if (addrH < 0x20) { //below $2000 A13 clear, /A13 set
|
|
//ADDRH(addrH | PPU_A13N_BYTE);
|
|
//Don't do weird stuff like above! logic inside macro expansions can have weird effects!!
|
|
addrH |= PPU_A13N_BYTE;
|
|
ADDRH(addrH);
|
|
} else { //above PPU $1FFF, A13 set, /A13 clear
|
|
ADDRH(addrH);
|
|
}
|
|
|
|
//set CHR /RD and /WR
|
|
CSRD_LO();
|
|
|
|
//set lower address bits
|
|
ADDRL(first); //doing this prior to entry and right after latching
|
|
NOP(); //adding extra NOP as it was needed on PRG
|
|
//gives longest delay between address out and latching data
|
|
|
|
for( i=0; i<=len; i++ ) {
|
|
//couple more NOP's waiting for data
|
|
if ( poll == FALSE ) {
|
|
NOP(); //one prob good enough considering the if/else
|
|
NOP();
|
|
} else {
|
|
usbPoll();
|
|
}
|
|
//latch data
|
|
DATA_RD(data[i]);
|
|
//set lower address bits
|
|
first ++;
|
|
ADDRL(first);
|
|
}
|
|
|
|
//return bus to default
|
|
CSRD_HI();
|
|
|
|
//return index of last byte read
|
|
return i;
|
|
}
|
|
|
|
|
|
/* Desc:NES DUAL PORT PPU Page Read with optional USB polling
|
|
* /A13 ignored
|
|
* if poll is true calls usbdrv.h usbPoll fuction
|
|
* this is needed to keep from timing out when double buffering usb data
|
|
* Pre: nes_init() setup of io pins
|
|
* num_bytes can't exceed 256B page boundary
|
|
* Post:address left on bus
|
|
* data bus left clear
|
|
* data buffer filled starting at first for len number of bytes
|
|
* Rtn: Index of last byte read
|
|
*/
|
|
uint8_t nes_dualport_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
|
|
{
|
|
uint8_t i;
|
|
|
|
//ignore /A13, board doesn't see it anyway
|
|
ADDRH(addrH);
|
|
|
|
//now that data bus is no longer needed,
|
|
//can enable data path out of cart
|
|
M2_HI();
|
|
ROMSEL_LO();
|
|
|
|
//set CHR /RD and /WR
|
|
CSRD_LO();
|
|
|
|
//set lower address bits
|
|
ADDRL(first); //doing this prior to entry and right after latching
|
|
NOP(); //adding extra NOP as it was needed on PRG
|
|
//gives longest delay between address out and latching data
|
|
|
|
for( i=0; i<=len; i++ ) {
|
|
//couple more NOP's waiting for data
|
|
if ( poll == FALSE ) {
|
|
NOP(); //one prob good enough considering the if/else
|
|
NOP();
|
|
} else {
|
|
usbPoll();
|
|
}
|
|
//latch data
|
|
DATA_RD(data[i]);
|
|
//set lower address bits
|
|
first ++;
|
|
ADDRL(first);
|
|
}
|
|
|
|
//return bus to default
|
|
CSRD_HI();
|
|
M2_LO();
|
|
ROMSEL_HI();
|
|
|
|
//return index of last byte read
|
|
return i;
|
|
}
|
|
|
|
|
|
|
|
/* Desc:NES MMC1 Write
|
|
* write to entirety of MMC1 register
|
|
* address selects register that's written to
|
|
* address must be >= $8000 where registers are located
|
|
* Pre: nes_init() setup of io pins
|
|
* MMC1 shift register has been reset by writting with D7 set
|
|
* bit7 must be clear, else the shift register will be reset
|
|
* Post:MMC1 register contains value provided
|
|
* address left on bus
|
|
* data left on bus, but pullup only
|
|
* Rtn: None
|
|
*/
|
|
void mmc1_wr( uint16_t addr, uint8_t data, uint8_t reset )
|
|
{
|
|
uint8_t i;
|
|
|
|
//reset shift register if requested
|
|
if( reset ) {
|
|
nes_cpu_rd(0x8000);
|
|
nes_cpu_wr(0x8000, 0x80);
|
|
}
|
|
|
|
//5 bits in register D0-4, so 5 total writes through D0
|
|
for( i=0; i<5; i++) {
|
|
//MMC1 ignores all but the first write, so perform a read first
|
|
nes_cpu_rd(addr);
|
|
nes_cpu_wr(addr, data);
|
|
data = data >> 1;
|
|
}
|
|
|
|
return;
|
|
}
|
|
|