330 lines
13 KiB
C
330 lines
13 KiB
C
#include <avr/io.h>
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//This file contains pinout translations from AVR names to "kazzo" names
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//this file also works to make all kazzo versions compatible and "alike"
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//=======================================================
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//History of PCB revsisions produced by InfiniteNesLives
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//=======================================================
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//
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// First printed circuit board version
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// only handful made (less than 10?)
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// Purple solder mask
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// Labeled "Kazzo PCB rev 3.0"
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// Dated 8/22/2011
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// * Only contained NES and Famicom connectors
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// * Had bug where USB data lines mixed up
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// -manually fixed during component assembly
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// * Naruko determined this should have still been v1 board
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// -due to it's overall design and conflicting with someother v3 board
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// * This was my first ever PCB design and one of the first
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// times designing something for the NES/FC. Looking
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// back at the design there were some very noob decisions...
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// * INPUT/OUTPUT differences:
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// EXP9 - PD1/LED jumper
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// when closed, PD1 controls NES EXP9 and LED
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// when open, EXP9 is floating PD1 only controls LED
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// NES EXP9 was connected to GND pin #16 on FC
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// -I must have thought that GND pin could serve
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// different purpose..
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// -Result is PD1 is shorted to GND when FC cart inserted
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// and jumper closed..
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// Believe I closed this jumper on units I shipped
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// prob should have left it open..
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// ALOG - EXP6 - DIGI jumper
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// another noob jumper decision...
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// ALOG is the MCU AREF pin which should be tied to VCC
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// -I thought it was an analog in apparently...
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// DIGI is EXP flip flop Q6 output
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// Best position for this jumper is EXP6-DIGI
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// ALOG pad should be tied to VCC with jumper..
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// Doing that would make it similar to future designs.
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// Don't think I shipped any with ALOG jumper closed
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// NES EXP6 is tied to Famicom pin 46 (Sound to RF)
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// Expansion port FlipFlop /OE - CLK
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// Aside from lame jumper design above, biggest difference
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// between this PCB version and future ones.
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// -EXP FF /OE controlled by MCU PD7
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// -EXP FF CLK controlled by MCU PC3
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// Future versions control both /OE and CLK with PD7
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// -this frees PC3 for user use
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// Both FlipFlops D i/p are driven by Data bus (PORT B)
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//
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//
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// Second printed circuit board version
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// only handful made (about a dozen?)
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// Purple solder mask
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// Labeled "Kazzo PCB rev 1.1"
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// Dated 8/22/2011
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// * Only contained NES and Famicom connectors
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// * Identical to version above aside from the following
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// * Corrected bug where USB data lines mixed up
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// * Changed silkscreen to v1.1 as suggested by naruko
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// * INPUT/OUTPUT differences:
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// -Same as version above as far as I know.
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//
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//
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// Third printed circuit board version
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// only handful made (about ten?) used primarily as SNES prototype
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// Green solder mask
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// Labeled "Retro programmer/dumper v1.2" "Kazzo 1.x"
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// Dated Apr 2013
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// * First version to add SNES connector along with NES & FC
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// * Removed noob jumpers from purple versions above.
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// -grouned FC pin16 as it should have been.
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// * INPUT/OUTPUT differences:
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// -EXP FF /OE still controlled by MCU PD7
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// -MCU PC7 controls both CLK on both FF's.
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// -EXP FF D inputs are PORTA
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// all other versions are driven by PORTB
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// This means you always have to clock both flipflops
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// Place desired value on PORTA/B respectively and clock with PD7
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// -PC3 is free for user use.
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// -SNES /RESET pin not controlled by PD0 (EXP0)
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// instead it's controlled by A20 (EXPFF Q4)
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// prevents putting INL SNES boards in program mode unless A20 is also low
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// pretty much makes flashing SNES boards a royal PITA/impossible
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// would have to free /RESET and wire to EXP0/PD0 to flash INL SNES board.
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//
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//
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//
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// Fourth printed circuit board version
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// First volume PCB run ~300 copies
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// Yellow solder mask
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// Labeled "Retro programmer/dumper v1.2b" "Kazzo 1.x"
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// Dated May 2013
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// * Includes NES, Famicom, & SNES connector
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// * SNES board must be removed from case and slid all the way to right
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// * Pitch offset on SNES connector makes it difficult to connect with original SNES boards.
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// -Connector designed to only provide support for INL SNES Hi/Lo-ROM boards.
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// * Care must be excersized not to insert SNES board backwards applying reverse power.
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// * Effectively Final circuit design after lessons learned on small batches that preceeded.
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// * INPUT/OUTPUT differences:
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// -EXP FF /OE & CLK controlled by MCU PD7
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// -MCU PC7 only controls CLK on ADDR HIGH FF.
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// -EXP & ADDRHI FF D inputs both on Data bus PORTB
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// -PC3 is free for user use.
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// -SNES /RESET pin controlled by PD0 (EXP0)
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// -Retains prev ver fixes, nothing funny going on with jumpers FC GND pin #16
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//
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//
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// Fifth printed circuit board version
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// Second volume PCB run ~500 copies
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// Yellow solder mask
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// Labeled "Retro programmer/dumper v1.2b" "Kazzo 1.x"
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// Dated OCT 2014
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// * Includes NES, Famicom, & SNES connector
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// * SNES connector setup/cautions just like the prev version.
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// * No significant changes from previous version.
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// -Changed MCU clock to Crystal instead of resonator in prev ver.
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// -Added screw mount holes, although not very well placed.
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// * INPUT/OUTPUT differences:
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// -None from previous version
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//
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//
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// Sixth printed circuit board version
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// Third volume PCB run in production as of 1NOV2016
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// Orange solder mask
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// Labeled "Retro programmer/dumper v1.4" "Kazzo 1.x"
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// Dated OCT 2016
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// * Includes NES, Famicom, & SNES connector
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// * SNES connector improvement to correct pitch issue with prev ver.
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// * Addition of PCT resettable fuse on incoming power.
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// -Provides protection to SNES boards inserted backwards.
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// * Rearrangement of BL/RUN switch and screw holes for better case design.
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// * Cut out buzzer pads (PD6) from under MCU which was never developed.
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// * INPUT/OUTPUT differences:
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// -None from previous version
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//
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#define LO 0x00
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#define HI 0xFF
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//#define TRUE 0x00
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//FALSE is ANYTHING but TRUE, the value signifies the error number
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//============================
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//ADDR[7:0] PORTA
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//============================
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//PORT DEFN
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#define ADDR_OUT PORTA
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#define ADDR_IN PINA
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#define ADDR_DDR DDRA
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//DDR-PORT MACROS
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#define ADDR_IP() ADDR_DDR = LO
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#define ADDR_OP() ADDR_DDR = HI
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#define ADDR_HI() ADDR_OUT = HI
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#define ADDR_LO() ADDR_OUT = LO
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//============================
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//DATA[7:0] PORTB
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//============================
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//PORT DEFN
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#define DATA_OUT PORTB
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#define DATA_IN PINB
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#define DATA_DDR DDRB
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//DDR-PORT MACROS
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#define DATA_IP() DATA_DDR = LO
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#define DATA_OP() DATA_DDR = HI
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#define DATA_HI() DATA_OUT = HI
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#define DATA_LO() DATA_OUT = LO
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//============================
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//CTL PORTC
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//============================
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//PORT DEFN
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#define CTL_OUT PORTC
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#define CTL_IN PINC
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#define CTL_DDR DDRC
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//DDR-PORT MACROS
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#define CTL_IP() CTL_DDR = LO
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// No CTL_OP() macro as some of these are inputs or bidir, best to individually assert as output
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#define CTL_HI() CTL_OUT = HI
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#define CTL_LO() CTL_OUT = LO
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//OLD CODE //AHL, AXL, are always output and high, unless individually asserted.
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// #define CTL_IP() CTL_DDR = 0b10001000// &= ((1<<AHL) | (1<<AXL))
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// #define CTL_OP() CTL_DDR = 0b10111111 //&= ~(1<<CICE); CTL_DDR |= ~((1<<AHL) | (1<<AXL) | (1<<CICE)) //CIRAM /CE is always input
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// #define CTL_HI() CTL_OUT |= ~((1<<AHL) | (1<<AXL))
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// //maintain these high unless individually asserted
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// #define CTL_LO() CTL_OUT &= ((1<<AHL) | (1<<AXL))
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//PIN DEFN
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#define M2 PC0 //NES, FC, & SNES (SYSCLK)
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#define ROMSEL PC1 //(aka PRG/CE) NES, FC, & SNES
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#define PRGRW PC2 //PRG R/W on NES & FC
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#define p_AXL PC3 //EXP FF CLK on purple boards
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#define FREE PC3 //Free pin on all other boards
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#define C_RD PC4 //NES & FC CHR /RD
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#define S_RD PC4 //SNES /RD
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#define C_WR PC5 //NES & FC CHR /WR
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#define S_WR PC5 //SNES /WR
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#define CICE PC6 //NES & FC CIRAM /CE, most carts are 2screen tying this to CHR A13 making this an I/P
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#define AHL PC7 //ADDR MID FF CLK per orig kazzo design
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#define g_AXL PC7 //Also EXP/ADDRHI FF CLK on green prototype
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//PIN MACROS
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#define M2_IP() CTL_DDR &= ~(1<<M2)
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#define M2_OP() CTL_DDR |= (1<<M2)
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#define M2_HI() CTL_OUT |= (1<<M2)
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#define M2_LO() CTL_OUT &= ~(1<<M2)
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//TODO read M2 PIN as input
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#define ROMSEL_IP() CTL_DDR &= ~(1<<ROMSEL)
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#define ROMSEL_OP() CTL_DDR |= (1<<ROMSEL)
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#define ROMSEL_HI() CTL_OUT |= (1<<ROMSEL)
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#define ROMSEL_LO() CTL_OUT &= ~(1<<ROMSEL)
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#define CICE_IP() CTL_DDR &= ~(1<<CICE)
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#define CICE_OP() CTL_DDR |= (1<<CICE)
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#define CICE_HI() CTL_OUT |= (1<<CICE)
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#define CICE_LO() CTL_OUT &= ~(1<<CICE)
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//#define PU_CICE() CTL_DDR &= ~(1<<CICE); CTL_OUT |= (1<<CICE);
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#define PRGRW_IP() CTL_OUT &= ~(1<<PRGRW)
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#define PRGRW_OP() CTL_OUT |= (1<<PRGRW)
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#define PRGRW_RD() CTL_OUT |= (1<<PRGRW) //HI for reads
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#define PRGRW_WR() CTL_OUT &= ~(1<<PRGRW) //LO for writes
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// //SNES copy cart needs CIRAM A10 and CIRAM /CE to be outputs
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// #define CC_OP() AUX_DDR |= (1<<CIA10); CTL_DDR |= (1<<CICE)
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// #define CC_IP() AUX_DDR &= ~(1<<CIA10); CTL_DDR &= ~(1<<CICE)
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//============================
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//AUX PORTD
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//============================
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//PORT DEFN
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#define AUX_OUT PORTD
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#define AUX_IN PIND
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#define AUX_DDR DDRD
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//DDR-PORT MACROS
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#define AUX_IP() AUX_DDR &= ((1<<USBP) | (1<<USBM)) //Don't touch USB pins!!!
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// No AUX_OP() macro as many of these are inputs or bidir, best to individually assert as output
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#define AUX_HI() AUX_OUT |= ~((1<<USBP) | (1<<USBM))
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#define AUX_LO() AUX_OUT &= ((1<<USBP) | (1<<USBM))
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//PIN DEFN
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#define EXP0 PD0 //NES EXP0
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#define FC_APU PD0 //FC Audio in cart from 2A03 APU
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#define TDO PD0 //CPLD JTAG on INL-ROM NES/FC boards released after ~Oct2016
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#define S_RST PD0 //SNES /RESET pin used for CPLD prgm/play mode and SRAM CE
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#define LED PD1 //LED on INL retro prog-dumper
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#define EXP9 PD1 //NES dual purposed pin
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#define USBP PD2 //USB D+ don't touch this pin!
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#define IRQ PD3 //Connected to NES, FC, & SNES
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#define USBM PD4 //USB D- don't touch this pin!
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#define CIA10 PD5 //NES & FC CIRAM A10 (aka VRAM A10)
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#define BL PD6 //Bootloader switch BL->GND, RUN->float
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#define p_XOE PD7 //EXP/ADDRHI FF /OE pin on purple and green boards
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#define AXLOE PD7 //EXP/ADDRHI FF CLK & /OE pin on final board versions
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//PIN MACROS
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// //EXP0 to only be pulled high because XO boards don't level shift EXP0
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// //EXP0_LO(); replace with EXP0_LO(); EXP0_OP();
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// //EXP0_HI(); replace with EXP0_IP(); EXP0_HI();
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// #define EXP0_IP() AUX_DDR &= ~(1<<EXP0)
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// #define EXP0_OP() AUX_DDR |= (1<<EXP0)
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// #define EXP0_HIGH() AUX_OUT |= (1<<EXP0)
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// #define EXP0_LOW() AUX_OUT &= ~(1<<EXP0)
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// #define EXP0_HI() EXP0_IP(); EXP0_HIGH(); NOP(); NOP(); NOP(); NOP();
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// #define EXP0_LO() EXP0_LOW(); EXP0_OP();
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#define ENABLE_LED() AUX_DDR |= (1<<LED)
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#define DISABLE_LED() AUX_DDR &= ~(1<<LED)
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#define LED_ON() AUX_OUT |= (1<<LED)
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#define LED_OFF() AUX_OUT &= ~(1<<LED)
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//#define SETUP_ADDR_X() AUX_DDR |= (1<<XOE)
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//#define DISABLE_ADDR_X() AUX_OUT |= (1<<XOE)
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//#define ENABLE_ADDR_X() AUX_OUT &= ~(1<<XOE)
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//
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//#define SETUP_AHL() CTL_DDR |= (1<<AHL); CTL_OUT |= (1<<AHL) //output high
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//#define SETUP_AXL() CTL_DDR |= (1<<AXL); CTL_OUT |= (1<<AXL) //output high
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//#define LATCH_AHL() CTL_OUT &= ~(1<<AHL); CTL_OUT |= (1<<AHL) //toggle low -> high
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//#define LATCH_AXL() CTL_OUT &= ~(1<<AXL); CTL_OUT |= (1<<AXL) //toggle low -> high
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// #define PRG_RD_PCE_HI() CTL_OUT |= (1<<PRW) | (1<<PCE)
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// #define PRG_WR_PCE_LO() CTL_OUT &= ~((1<<PRW) | (1<<PCE))
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//
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// //#define SNES_RD_SEL_HI() CTL_OUT |= (1<<CRD) | (1<<PCE)
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// #define SNES_WR_SEL_LO() CTL_OUT &= ~((1<<CWR) | (1<<PCE))
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// #define SNES_RD_SEL_LO() CTL_OUT &= ~((1<<CRD) | (1<<PCE))
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// #define SNES_CTL_HI() CTL_OUT |= (1<<CWR) | (1<<CRD) | (1<<PCE)
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// #define CC_CTL_HI() CTL_OUT |= (1<<PRW) | (1<<CICE); AUX_OUT |= (1<<CIA10)
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// //#define SNES_CTL_LO() CTL_OUT &= ~((1<<CWR) | (1<<CRD) | (1<<PCE))
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//
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// #define CHR_OEN() CTL_OUT |= (1<<CRD)
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// #define CHR_OE() CTL_OUT &= ~(1<<CRD)
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// #define CHR_WEN() CTL_OUT |= (1<<CWR) //Not-able (high)
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// #define CHR_WE() CTL_OUT &= ~(1<<CWR) //Enabled (low)
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//
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// #define CC_OEN() AUX_OUT |= (1<<CIA10)
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// #define CC_OE() AUX_OUT &= ~(1<<CIA10)
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// #define CC_WEN() CTL_OUT |= (1<<PRW) //Not-able (high)
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// #define CC_WE() CTL_OUT &= ~(1<<PRW) //Enabled (low)
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//
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// #define CHR_RD() CHR_WEN(); CHR_OE();
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// #define CHR_WR() CHR_OEN(); CHR_WE(); // /OE-hi /WE-lo
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//
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// // /WE-hi /OE-lo
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// // PRG RW hi, CIRAMA10 lo
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// #define CC_RD() CC_WEN(); CC_OE();
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// #define CC_WR() CC_OEN(); CC_WE();
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// //CIRAM A10 hi, PRGRW lo
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// // /OE-hi /WE-lo
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