292 lines
9.9 KiB
C
292 lines
9.9 KiB
C
#include <avr/io.h>
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#include "logic.h"
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#include "pinport.h"
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//This file is generated from pinport.h
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//the close relationship between these two files must be kept in mind when making changes.
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//This file is also very dependent on macro definitions in host app.
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//the host app pinport.h was generated from this file, so any changes here must be forwarded.
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/* Desc:Function takes an opcode which was transmitted via USB
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* then decodes it to call designated macro.
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* Pre: Macro must be defined in firmware pinport.h
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* opcode must align with host pinport.h otherwise who knows what you're calling
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* Post:Macro call complete.
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* Rtn: SUCCESS if opcode found, ERROR_UNKNOWN_OPCODE if opcode not present.
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*/
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uint8_t pinport_macro( uint8_t opcode )
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{
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//these should be simple macros only for now
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//ie only changes one pin/port, macro doesn't call other macros yet
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//made exception to this rule for EXP0 since doesn't vary on board versions
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switch (opcode) {
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//============================
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//ADDR[7:0] PORTA
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//============================
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//DDR-PORT MACROS
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case 0: ADDR_IP(); break;
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case 1: ADDR_OP(); break;
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case 2: ADDR_LO(); break;
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case 3: ADDR_HI(); break;
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//============================
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//DATA[7:0] PORTB
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//============================
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//DDR-PORT MACROS
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case 4: DATA_IP(); break;
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case 5: DATA_OP(); break;
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case 6: DATA_LO(); break;
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case 7: DATA_HI(); break;
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//============================
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//CTL PORTC
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//============================
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//DDR-PORT MACROS
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case 8: CTL_IP(); break;
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// No CTL_OP() macro as some of these are inputs or bidir, best to individually assert as output
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case 9: CTL_LO(); break;
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case 10: CTL_HI(); break;
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//PIN MACROS
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case 11: M2_IP(); break;
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case 12: M2_OP(); break;
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case 13: M2_LO(); break;
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case 14: M2_HI(); break;
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//TODO read M2 PIN as input
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case 15: ROMSEL_IP(); break;
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case 16: ROMSEL_OP(); break;
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case 17: ROMSEL_LO(); break;
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case 18: ROMSEL_HI(); break;
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case 19: CICE_IP(); break;
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case 20: CICE_OP(); break;
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case 21: CICE_LO(); break;
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case 22: CICE_HI(); break;
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case 23: PRGRW_IP(); break;
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case 24: PRGRW_OP(); break;
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case 25: PRGRW_WR(); break; //LO for writes
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case 26: PRGRW_RD(); break; //Hi for reads
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//give each def different version numbers to detect errors
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//where command given to board which doesn't have that function
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#ifdef p_AXL //purple boards only
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case 27: p_AXL_IP(); break;
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case 28: p_AXL_OP(); break;
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case 29: p_AXL_lo(); break; //Don't recommend calling lo/hi, use CLK instead
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case 30: p_AXL_hi(); break;
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//AXL_CLK assumes AXL was previously left in default low state
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//XX: AXL_CLK() p_AXL_hi(); p_AXL_lo(); //same name and convention on final design
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#else //Green and final design
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case 31: FREE_IP(); break;
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case 32: FREE_OP(); break;
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case 33: FREE_LO(); break;
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case 34: FREE_HI(); break;
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#endif
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case 35: CSRD_IP(); break;
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case 36: CSRD_OP(); break;
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case 37: CSRD_LO(); break;
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case 38: CSRD_HI(); break;
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case 39: CSWR_IP(); break;
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case 40: CSWR_OP(); break;
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case 41: CSWR_LO(); break;
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case 42: CSWR_HI(); break;
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case 43: CICE_IP(); break;
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case 44: CICE_OP(); break;
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case 45: CICE_LO(); break;
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case 46: CICE_HI(); break;
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#ifdef g_AXHL
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case 47: g_AXHL_IP(); break;
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case 48: g_AXHL_OP(); break;
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case 49: g_AXHL_lo(); break; //Don't recommend calling these as AXHL should be left low
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case 50: g_AXHL_hi(); break; //That way AXHL_CLK(); is always effective
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//XX: AXHL_CLK() g_AXHL_hi(); g_AXHL_lo();
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#else //purple and final design
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case 51: AHL_IP(); break;
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case 52: AHL_OP(); break;
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case 53: AHL_lo(); break; //Don't recommend calling these as AHL should be left low
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case 54: AHL_hi(); break; //That way AHL_CLK(); is always effective
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//XX: AHL_CLK() AHL_hi(); AHL_lo();
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#endif
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//============================
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//AUX PORTD
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//============================
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//DDR-PORT MACROS
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case 55: AUX_IP(); break; //Don't touch USB pins!!!
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// No AUX_OP(); macro as many of these are inputs or bidir, best to individually assert as output
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case 56: AUX_LO(); break;
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case 57: AUX_HI(); break;
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//PIN MACROS
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//lower case aren't meant to be called unless certain pin is 5v tolerant
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case 58: EXP0_ip(); break;
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case 59: EXP0_op(); break;
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case 60: EXP0_lo(); break; //Don't call this assuming EXP0 DDR is set to o/p
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case 61: EXP0_hi(); break; //Don't call this unless you're certain pin is 5v tolerant
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//User options pull up, force low, and float
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case 62: EXP0_LO(); break; //Sets low then DDR to o/p
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case 63: EXP0_PU(); break; //maybe add some NOP(); to allow time for pull up
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case 64: EXP0_FLT(); break; //Set to i/p w/o pullup
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case 65: LED_IP(); break;
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case 66: LED_OP(); break;
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case 67: LED_OFF(); break;
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case 68: LED_ON(); break;
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case 69: IRQ_IP(); break;
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case 70: IRQ_OP(); break;
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case 71: IRQ_LO(); break;
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case 72: IRQ_HI(); break;
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case 73: CIA10_IP(); break;
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case 74: CIA10_OP(); break;
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case 75: CIA10_LO(); break;
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case 76: CIA10_HI(); break;
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case 77: BL_IP(); break;
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case 78: BL_OP(); break;
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case 79: BL_LO(); break;
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case 80: BL_HI(); break;
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#ifndef pg_XOE //FINAL_DESIGN
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case 81: AXLOE_IP(); break;
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case 82: AXLOE_OP(); break;
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//Caution AXL_CLK() relies on EXPFF_OP() to be called beforehand
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// Think of it like you must enable the output before you can clock it.
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// Floating EXPFF also happens to clock it. Think of it like it looses it's value if disabled.
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//XX: AXL_CLK() EXPFF_FLT(); EXPFF_OP(); //same name and convention as purple
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#else //purple and green versions
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case 83: XOE_IP(); break;
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case 84: XOE_OP(); break;
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#endif
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//Same definition on all board versions
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//Only need to be cognizant that AXL_CLK won't work if EXPFF_FLT was called beforehand
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//This is only an issue on final design, so an error here should only cause probs on final design
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//Net effect is it it works on final design should be fine on other versions which is the goal
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case 85: EXPFF_OP(); break; //FF /OE pin low->enable o/p
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case 86: EXPFF_FLT(); break; //FF /OE pin high->disable o/p
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//AXL_CLK this is similar between purple and green versions, just on a different pin.
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//green boards don't have an AXL_CLK nor a AHL_CLK, as the two are combined.
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//green boards must resolve this in software storing value of FF's so can have the effect
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//of only clocking one of them.
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//#ifdef g_AXHL
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//case XX: AXHL_CLK(); break; //don't want to call this as software AXL/AHL don't track
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//case 87: software_AXL_CLK(); break;
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//case 88: software_AHL_CLK(); break;
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//#else
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//these two cases covers all designs with macro calling sofware versions for green board.
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case 87: AXL_CLK(); break;
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case 88: AHL_CLK(); break;
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//#endif
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//these work fine in hardware for purple and final.
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//green had to separate these two with software.
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default:
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//macro doesn't exist on this PCB version
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return ERROR_UNKWN_PINP_OPCODE;
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}
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return SUCCESS;
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}
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#ifdef GREEN_KAZZO
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/* Desc:
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* other board versions have PORTB "DATA" feed into both FF's
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* this board feeds EXP FF with PORTA "ADDR" instead
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* goal is to make board versions 'identical'
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* to do this we assume higher level functions will have already
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* placed desired latch value on PORTB "DATA_OUT"
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* we need to juggle this data around and not stomp on anything
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* Pre: DATA_OP() set
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* curAHLaddr set by software_AHL_CLK
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* DATA_OUT contains desired value to be latched by EXP FF
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* AXHL might not be set as O/P
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* AXHL might not be low ready for AXHL_CLK
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* Post:Both FF's have desired value latched
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* ADDR_OP() left set
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* curAXLaddr updated for use by software_AHL_CLK
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* DATA_OUT and ADDR_OUT replaced with original values
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* AXHL left as O/P and ready for subsequent CLK
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*/
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//these variables are updated each time the FF's are clocked
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//that way we can retain the value of other FF as both must be clocked at once
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static uint8_t curAHLaddr;
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static uint8_t curAXLaddr;
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void software_AXL_CLK()
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{
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//first store current DATA & ADDR values
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uint8_t curAXLaddr = DATA_OUT; //This is desired AXL value
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uint8_t orig_addr = ADDR_OUT; //PORTA
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//Put current AHL latched value on DATA as that's where it'll be relatched
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//software_AHL_CLK function is one to maintain this value
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DATA_OUT = curAHLaddr;
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//set ADDR as O/P and place desired value on bus
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ADDR_OP(); //should already be set, but in case not
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ADDR_OUT = curAXLaddr;
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//Clock both latches
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g_AXHL_OP(); //can't be sure "AHL" is OP as assumption is AXL will be used as latch
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g_AXHL_lo(); //can't be sure it's low either
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AXHL_CLK(); //clock values
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//finally restore original DATA & ADDR values
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DATA_OUT = curAXLaddr;
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ADDR_OUT = orig_addr;
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}
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/* Desc: Same premise as software_AXL_CLK above.
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* this is a little simpler as data has already been feed with AHL value.
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* just need to make sure AXL latch doesn't get corrupted.
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* Pre: DATA_OP() set
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* curAXLaddr set by software_AXL_CLK
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* DATA_OUT contains desired value to be latched by ADDRMID FF
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* AXHL is already set to O/P
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* AXHL already low ready for AXHL_CLK
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* Post:Both FF's have desired value latched
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* curAHLaddr updated for use by software_AXL_CLK
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* DATA_OUT and ADDR_OUT replaced with original values
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* AXHL left as O/P and ready for subsequent CLK
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*/
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void software_AHL_CLK()
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{
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//first store current DATA & ADDR values
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uint8_t curAHLaddr = DATA_OUT; //This is desired AHL value (store it for other function's use)
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uint8_t orig_addr = ADDR_OUT; //PORTA
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//Desired AHL latch value should have already been placed on DATA_OUT.
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//set ADDR as O/P and place curAXLaddr on bus other function should have updated it last latch
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ADDR_OP(); //should already be set, but in case not
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ADDR_OUT = curAXLaddr;
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//Clock both latches
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//Can assume AHL is OP as other versions would require it to latch AHL
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//Can also assume it was left low, if not causes issues in all board versions
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AXHL_CLK(); //clock values
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//finally restore original DATA & ADDR values
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//never changed: DATA_OUT = curAHLaddr;
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ADDR_OUT = orig_addr;
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}
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#endif //GREEN_KAZZO
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