964 lines
24 KiB
C
964 lines
24 KiB
C
#include "flash.h"
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uint8_t write_page( uint8_t addrH, buffer *buff, write_funcptr wr_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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wr_func( ((addrH<<8)| n), buff->data[n] );
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//write function returns when it's complete or errors out
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n++;
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cur++;
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}
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buff->cur_byte = n;
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//TODO error check/report
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return SUCCESS;
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}
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uint8_t write_page_old( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlock2, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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wr_func( unlock1, 0xAA );
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wr_func( unlock2, 0x55 );
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wr_func( unlock1, 0xA0 );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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// if (read == buff->data[n]) {
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n++;
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cur++;
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// LED_IP_PU();
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// LED_LO();
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// } else {
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// nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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// nes_cpu_wr(0x8000, bank); //outer bank
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// nes_cpu_wr(0x5000, 0x00); //chr reg select act like cnrom
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// LED_OP();
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// LED_HI();
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// }
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlock2, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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//select first bank for unlock sequence
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//needs to be written to bank table!
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// nes_cpu_wr( (0xCC84), 0x00 );
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// nes_cpu_wr( (0xE473), 0x00 );
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// nes_cpu_wr( (0xC000), 0x00 );
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nes_cpu_wr( (0xFD69), 0x00 );
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//wr_func( 0x5555, 0xAA );
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wr_func( unlock1, 0xAA );
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//wr_func( 0x2AAA, 0x55 );
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wr_func( unlock2, 0x55 );
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//wr_func( 0x5555, 0xA0 );
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wr_func( unlock1, 0xA0 );
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//now need to select bank for the actual write!
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//but this write can't be applied to the PRG-ROM
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// nes_cpu_wr( (0xCC84+bank), bank );
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// nes_cpu_wr( (0xE473+bank), bank );
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// nes_cpu_wr( (0x8000+bank), bank );
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//nes_cpu_wr( (0xC000+bank), bank );
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// nes_cpu_wr( (0xFFC0+bank), bank );
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nes_cpu_wr( (0xFD69+bank), bank );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_bank_map30( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlock2, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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//select first bank for unlock sequence
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//wr_func( 0x5555, 0xAA );
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nes_cpu_wr( 0xC000, 0x01 );
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wr_func( unlock1, 0xAA );
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//wr_func( 0x2AAA, 0x55 );
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nes_cpu_wr( 0xC000, 0x00 );
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wr_func( unlock2, 0x55 );
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//wr_func( 0x5555, 0xA0 );
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nes_cpu_wr( 0xC000, 0x01 );
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wr_func( unlock1, 0xA0 );
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//now need to select bank for the actual write!
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nes_cpu_wr( 0xC000, bank );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_mmc1( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlock2, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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mmc1_wr(0x8000, 0x10, 0); //32KB mode
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//IDK why, but somehow only the first byte gets programmed when ROM A14=1
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//so somehow it's getting out of 32KB mode for follow on bytes..
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//even though we reset to 32KB mode after the corrupting final write
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wr_func( unlock1, 0xAA );
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wr_func( unlock2, 0x55 );
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wr_func( unlock1, 0xA0 );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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//writes to flash are to $8000-FFFF so any register could have been corrupted and shift register may be off
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//In reality MMC1 should have blocked all subsequent writes, so maybe only the CHR reg2 got corrupted..?
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mmc1_wr(0x8000, 0x10, 1); //32KB mode
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mmc1_wr(0xE000, bank, 0); //reset shift register, and bank register
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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mmc1_wr(0x8000, 0x10, 1); //32KB mode
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mmc1_wr(0xE000, bank, 0); //reset shift register, and bank register
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_a53( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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//enter unlock bypass mode
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wr_func( 0x8AAA, 0xAA );
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wr_func( 0x8555, 0x55 );
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wr_func( 0x8AAA, 0x20 );
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while ( cur <= buff->last_idx ) {
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//TODO FIX THIS! It shouldn't be needed!
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//but for some reason the mapper is loosing it's setting for $5000 register to
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//permit flash writes. Many writes go through, but at somepoint it gets lost..
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//maybe the best fix it to require address to be equal to $5555 to write to flash enable register..
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//but for now, this rewrite hack solves the issue.
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nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
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//AVR didn't need this patch so maybe is a speed issue
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//stmadapter didn't have problems either..
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//added time delay before m2 rising edge and it didn't change anything for stm6
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// curaddresswrite( 0xA0 ); //gained ~3KBps (59.13KBps) inl6 with v3.0 proto
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wr_func( ((addrH<<8)| n), 0xA0 );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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//kaz6 final needs a retry, but proto doesn't...
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nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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nes_cpu_wr(0x8000, bank); //outer bank
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nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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//exit unlock bypass mode
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wr_func( 0x8000, 0x90 );
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wr_func( 0x8000, 0x00 );
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//reset the flash chip, supposed to exit too
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wr_func( 0x8000, 0xF0 );
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return SUCCESS;
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}
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uint8_t write_page_tssop( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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//enter unlock bypass mode
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wr_func( 0x8AAA, 0xAA );
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wr_func( 0x8555, 0x55 );
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wr_func( 0x8AAA, 0x20 );
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while ( cur <= buff->last_idx ) {
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// curaddresswrite( 0xA0 ); //gained ~3KBps (59.13KBps) inl6 with v3.0 proto
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wr_func( ((addrH<<8)| n), 0xA0 );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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//kaz6 final needs a retry, but proto doesn't...
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// nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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// nes_cpu_wr(0x8000, bank); //outer bank
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// nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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//exit unlock bypass mode
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wr_func( 0x8000, 0x90 );
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wr_func( 0x8000, 0x00 );
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//reset the flash chip, supposed to exit too
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wr_func( 0x8000, 0xF0 );
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return SUCCESS;
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}
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uint8_t write_page_chr( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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wr_func( 0x1555, 0xAA );
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wr_func( 0x0AAA, 0x55 );
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wr_func( 0x1555, 0xA0 );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//TODO verify byte is value that was trying to be flashed
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//move on to next byte
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//n++;
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//cur++;
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_chr_cnrom( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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nes_cpu_wr( 0x8000, 0x02 );
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wr_func( 0x1555, 0xAA );
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nes_cpu_wr( 0x8000, 0x01 );
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wr_func( 0x0AAA, 0x55 );
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nes_cpu_wr( 0x8000, 0x02 );
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wr_func( 0x1555, 0xA0 );
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nes_cpu_wr( 0x8000, bank );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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nes_cpu_wr( 0x8000, bank );
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//TODO verify byte is value that was trying to be flashed
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//move on to next byte
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//n++;
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//cur++;
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if (read == buff->data[n]) {
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// n++;
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// cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_chr_cdream( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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nes_cpu_wr(0x8000, 0x20);
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wr_func( 0x1555, 0xAA );
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nes_cpu_wr(0x8000, 0x10);
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wr_func( 0x0AAA, 0x55 );
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nes_cpu_wr(0x8000, 0x20);
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wr_func( 0x1555, 0xA0 );
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nes_cpu_wr(0x8000, bank<<4);
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//TODO verify byte is value that was trying to be flashed
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//move on to next byte
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//n++;
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//cur++;
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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return SUCCESS;
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}
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uint8_t write_page_dualport( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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//enter unlock bypass mode
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wr_func( 0x0AAA, 0xAA );
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wr_func( 0x0555, 0x55 );
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wr_func( 0x0AAA, 0x20 );
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while ( cur <= buff->last_idx ) {
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wr_func( ((addrH<<8)| n), 0xA0 );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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do {
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usbPoll();
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read = rd_func((addrH<<8)|n);
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} while( read != rd_func((addrH<<8)|n) );
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//TODO verify byte is value that was trying to be flashed
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//move on to next byte
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//n++;
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//cur++;
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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buff->cur_byte = n;
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//exit unlock bypass mode
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wr_func( 0x0000, 0x90 );
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wr_func( 0x0000, 0x00 );
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//reset the flash chip, supposed to exit too
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wr_func( 0x0000, 0xF0 );
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return SUCCESS;
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}
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//#define PRGM_MODE() swim_wotf(SWIM_HS, 0x500F, 0x40)
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//#define PLAY_MODE() swim_wotf(SWIM_HS, 0x500F, 0x00)
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//#define PRGM_MODE() EXP0_LO()
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//#define PLAY_MODE() EXP0_HI()
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#define PRGM_MODE() NOP()
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#define PLAY_MODE() NOP()
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uint8_t write_page_snes( uint8_t bank, uint8_t addrH, buffer *buff, write_funcptr wr_func, read_funcptr rd_func )
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{
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uint16_t cur = buff->cur_byte;
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uint8_t n = buff->cur_byte;
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uint8_t read;
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#ifdef AVR_CORE
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wdt_reset();
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#endif
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//set to program mode for first entry
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//EXP0_LO();
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//swim_wotf(SWIM_HS, 0x500F, 0x40)
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PRGM_MODE();
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//; TODO I don't think all these NOPs are actually needed, but they work and don't seem to significantly affect program time on stm32
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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//enter unlock bypass mode
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wr_func( 0x8AAA, 0xAA );
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wr_func( 0x8555, 0x55 );
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wr_func( 0x8AAA, 0x20 );
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while ( cur <= buff->last_idx ) {
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//write unlock sequence
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//unlocked wr_func( 0x0AAA, 0xAA );
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//unlocked wr_func( 0x0555, 0x55 );
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//wr_func( 0x0000, 0xA0 );
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snes_rom_wr_cur_addr( 0xA0 ); //gained ~3KBps (59.13KBps) inl6 with v3.0 proto
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wr_func( ((addrH<<8)| n), buff->data[n] );
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//wr_func( ((addrH<<8)| n), cur_data ); //didn't actually speed up
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//Targetting 2MByte 16mbit flash which doesn't have buffered writes
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//currently have average flash speed of 21.05KBps going to start removing some of these NOPs
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//and optimizing flash routine to get time down.
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//exit program mode
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// EXP0_HI();
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PLAY_MODE();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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//pre-fetch next byte of data
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//cur_data = buff->data[n+1];
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#ifdef AVR_CORE
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wdt_reset();
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#endif
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//wait for byte to flash
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// do {
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// usbPoll();
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// read = rd_func((addrH<<8)|n);
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//
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// //} while( read != rd_func((addrH<<8)|n) );
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// } while( read != buff->data[n] );
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//this can cause things to hang on failed programs..
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//need a smarter flash polling algo, kind of a pain because we don't have
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//a good way to toggle /OE or /CE quickly on v3 SNES boards
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usbPoll();
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read = rd_func((addrH<<8)|n);
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//prepare for upcoming write cycle, or allow for a polling read
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//EXP0_LO();
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PRGM_MODE();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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//First check if already outputting final data
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if (read != buff->data[n] ) {
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//if not, lets see if toggle is occuring
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//EXP0_HI();
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PLAY_MODE();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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while( read != rd_func((addrH<<8)|n) ){
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//EXP0_LO();
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PRGM_MODE();
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NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP();
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NOP(); NOP(); NOP(); NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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//EXP0_HI();
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PLAY_MODE();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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read = rd_func((addrH<<8)|n);
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}
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//prepare for upcoming write cycle
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//EXP0_LO();
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PRGM_MODE();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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NOP();
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}
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// //IDK why, but AVR will exit early sometimes
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// //without this second check, ~20 errors per 32KByte on SNES v3.0
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// //All error bytes are 0xFF instead of true data
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// //may need a smarter flash polling routine..
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// //Tried to add extra delay to read algo, and didn't change anything
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// //Also have decent trust in read routine as it's comparable to page read
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// //which works flawlessly for dumps. So think it has to do with flashing specifically...
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// //Hmm maybe the avr is missing a read.. flash /CE, /OE, and /WE never toggle
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// //so why would flash polling output different data between polls..?
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// //Ahh this is the issue, adding the code below only adds delay which gives flash
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// //enough time to complete write.
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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n++;
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cur++;
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// if (read == buff->data[n]) {
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// //n++;
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// //cur++;
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// LED_IP_PU();
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// LED_LO();
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// } else {
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// LED_OP();
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// LED_HI();
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// }
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}
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buff->cur_byte = n;
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//exit unlock bypass mode
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wr_func( 0x8000, 0x90 );
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wr_func( 0x8000, 0x00 );
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//reset the flash chip, supposed to exit too
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wr_func( 0x8000, 0xF0 );
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//exit program mode
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//EXP0_HI();
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PLAY_MODE();
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return SUCCESS;
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}
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/* Desc:Flash buffer contents on to cartridge memory
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* Pre: buffer elements must be updated to designate how/where to flash
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* buffer's cur_byte must be cleared or set to where to start flashing
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* mapper registers must be initialized
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* Post:buffer page flashed/programmed to memory.
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* Rtn: SUCCESS or ERROR# depending on if there were errors.
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*/
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uint8_t flash_buff( buffer *buff ) {
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uint8_t addrH = buff->page_num; //A15:8 while accessing page
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uint8_t bank;
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//First need to initialize mapper register bits
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//Perhaps this only needs to be done on first buffer though..?
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//Actually think this is best handled from buffer.c in operation == STARTFLASH
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//TODO use mapper to set mapper controlled address bits
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//need to calculate current bank and addrH
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//TODO set unlock addresses based on what works for that mapper and how it's banks are initialized
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//use mem_type to set addrH/X as needed for dump loop
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//also use to get read function pointer
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switch ( buff->mem_type ) {
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case PRGROM: //$8000
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if (buff->mapper == NROM) {
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//write_page_old( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
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write_page( (0x80+addrH), buff, nrom_prgrom_flash_wr);
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}
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if (buff->mapper == MMC1) {
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//write bank value
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//page_num shift by 6 bits A15 >> A9(1)
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bank = (buff->page_num)>>6; //LSbit doesn't matter in 32KB mode
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bank &= 0x0F; //only 4 bits in PRG register
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mmc1_wr(0x8000, 0x10, 1); //ensure 32KB mode
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mmc1_wr(0xE000, bank, 0); //write bank to PRG-ROM bank register
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//TODO SXROM/SUROM require writting PRG-ROM MSb of address to CHR registers
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write_page_mmc1( bank, (0x80 | addrH), 0xD555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
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}
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if (buff->mapper == UxROM) {
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//addrH &= 0b1011 1111 A14 must always be low
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addrH &= 0x3F;
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addrH |= 0x80; //A15 doesn't apply to exp0 write, but needed for read back
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//write bank value
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//page_num shift by 6 bits A14 >> A8(0)
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bank = buff->page_num >> 6;
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//bank gets written inside flash algo
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write_page_bank( bank, addrH, 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
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}
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if (buff->mapper == MMC3) {
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//Latest method used here!
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//leave the host responsible for init & banking
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//we just need to call a page write algo and give it mmc3_prgrom_flash_wr function
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//think of this only as an 8KB ROM
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//MMC3 flash writes are always $8000-9FFF, but the host arranges this
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write_page( (0x80+addrH), buff, mmc3_prgrom_flash_wr);
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}
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if (buff->mapper == MM2) {
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//addrH &= 0b1011 1111 A14 must always be low
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addrH &= 0x3F;
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addrH |= 0x80; //A15 doesn't apply to exp0 write, but needed for read back
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//write bank value
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//page_num shift by 6 bits A14 >> A8(0)
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bank = buff->page_num >> 6;
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//bank gets written inside flash algo
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write_page_bank( bank, addrH, 0x5555, 0x2AAA, buff, disc_push_exp0_prgrom_wr, nes_cpu_rd );
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}
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if (buff->mapper == MAP30) {
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//addrH &= 0b1011 1111 A14 must always be low
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addrH &= 0x3F;
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addrH |= 0x80;
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//write bank value
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//page_num shift by 6 bits A14 >> A8(0)
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bank = buff->page_num >> 6;
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//bank gets written inside flash algo
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write_page_bank_map30( bank, addrH, 0x9555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
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}
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//if ((buff->mapper == BxROM) || (buff->mapper == CDREAM)) {
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//new method uses same algo as NROM, host handles all the banking!
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// //write bank value
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// //page_num shift by 7 bits A15 >> A8(0)
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// bank = buff->page_num >> 7;
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// //Lizard banktable location
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// nes_cpu_wr( (0xFF94+bank), bank );
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// //hh85
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// //nes_cpu_wr( (0xFFE0+bank), bank );
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// //Mojontales
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// //nes_cpu_wr( 0x800C, 0x00); //select first bank (only bank with table)
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// //nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank
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// write_page_old( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
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//}
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if (buff->mapper == CNINJA) {
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//addrH &= 0b1001 1111 A14-13 must always be low
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addrH &= 0x1F;
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addrH |= 0x80;
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//write bank value
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//page_num shift by 5 bits A13 >> A8(0)
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bank = buff->page_num >> 5;
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nes_cpu_wr( (0x6000), 0xA5 ); //select desired bank
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nes_cpu_wr( (0xFFFF), bank ); //select desired bank
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write_page_old( 0, addrH, 0xD555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
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}
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if (buff->mapper == A53) {
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//write bank value to bank table
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//page_num shift by 7 bits A15 >> A8(0)
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bank = (buff->page_num)>>7;
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//Setup as CNROM, then scroll through outer banks.
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//cpu_wr(0x5000, 0x80); //reg select mode
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// xxSSPPMM SS-size: 0-32KB, PP-prg mode: 0,1 32KB, MM-mirror
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//cpu_wr(0x8000, 0b00000000); //reg value 256KB inner, 32KB banks
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nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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nes_cpu_wr(0x8000, bank); //outer bank
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nes_cpu_wr(0x5000, 0x54); //chr reg select act like CNROM & enable flash writes
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//need to use standard CPU writes
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//write_page_old( 0, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd );
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//break;
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//WORKS PLCC Action53:
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//had problems later not all bytes getting programmed..
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//write_page_old( bank, (0x80 | addrH), 0xD555, 0xAAAA, buff, nes_cpu_wr, nes_cpu_rd );
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//TSSOP-28 action53:
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write_page_a53( bank, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd );
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}
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if (buff->mapper == EZNSF) {
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//addrH &= 0b1000 1111 A14-12 must always be low
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addrH &= 0x8F;
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//write bank value to bank table
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//page_num shift by 4 bits A12 >> A8(0)
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bank = (buff->page_num)>>4;
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nes_cpu_wr(0x5000, bank); //bank @ $8000-8FFF
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write_page_tssop( bank, (0x80 | addrH), buff, nes_cpu_wr, nes_cpu_rd );
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}
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break;
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case CHRROM: //$0000
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if (buff->mapper == NROM) {
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//write_page_chr( 0, addrH, buff, nes_ppu_wr, nes_ppu_rd );
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write_page( addrH, buff, nrom_chrrom_flash_wr);
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}
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if (buff->mapper == CNROM) {
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//cur_bank and bank_table must be set in nes.c prior to calling
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write_page( addrH, buff, cnrom_chrrom_flash_wr);
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}
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if (buff->mapper == MMC3) {
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//Latest method used here!
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//leave the host responsible for init & banking
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//we just need to call a page write algo and give it mmc3_prgrom_flash_wr function
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//think of this only as an 8KB ROM
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//MMC3 flash writes are always $8000-9FFF
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write_page( addrH, buff, mmc3_chrrom_flash_wr);
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}
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if (buff->mapper == CDREAM) {
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// //select bank
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// //8KB banks $0000-1FFF
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// //page_num shift by 5 bits A13 >> A8(0)
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// bank = (buff->page_num)>>5;
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//
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// //write bank to register
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// //done inside write routine
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// //nes_cpu_wr(0x8000, bank<<4);
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//
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// addrH &= 0x1F; //only A12-8 are directly addressable
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// write_page_chr_cdream( bank, addrH, buff, nes_ppu_wr, nes_ppu_rd );
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write_page( addrH, buff, cdream_chrrom_flash_wr);
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}
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if (buff->mapper == DPROM) {
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//select bank
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//8KB banks $0000-1FFF
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//page_num shift by 5 bits A13 >> A8(0)
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bank = (buff->page_num)>>5;
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//write bank to register
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nes_ppu_wr(0x3FFF, bank);
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addrH &= 0x1F; //only A12-8 are directly addressable
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write_page_dualport( 0, addrH, buff, nes_dualport_wr, nes_dualport_rd );
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}
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break;
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case PRGRAM:
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write_page( addrH+0x60, buff, nes_cpu_wr);
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break;
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case SNESROM:
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if (buff->mapper == LOROM_5VOLT) {
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//LOROM banks start at $XX:8000
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write_page( addrH+0x80, buff, snes_5v_flash_wr);
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}
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if (buff->mapper == HIROM_5VOLT) {
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//HIROM banks start at $XX:0000
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write_page( addrH, buff, snes_5v_flash_wr);
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}
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if (buff->mapper == LOROM_3VOLT) {
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//LOROM banks start at $XX:8000
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write_page( addrH+0x80, buff, snes_3v_flash_wr);
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}
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if (buff->mapper == HIROM_3VOLT) {
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//HIROM banks start at $XX:0000
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write_page( addrH, buff, snes_3v_flash_wr);
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}
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if (buff->mapper == LOROM) {
|
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addrH |= 0x80; //$8000 LOROM space
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//need to split page_num
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//A14-8 page_num[7-0]
|
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//A15 high (LOROM)
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//A23-16 page_num[14-8]
|
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bank = (buff->page_num)>>7;
|
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//clear any reset state
|
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//EXP0_HI();
|
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HADDR_SET( bank );
|
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write_page_snes( 0, addrH, buff, snes_rom_wr, snes_rom_rd );
|
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}
|
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if (buff->mapper == HIROM) {
|
|
//need to split page_num
|
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//A15-8 page_num[7-0]
|
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//A21-16 page_num[13-8]
|
|
//A22 high (HIROM)
|
|
//A23 ~page_num[14] (bank CO starts first half, bank 40 starts second)
|
|
bank = ((((buff->page_num)>>8) | 0x40) & 0x7F);
|
|
HADDR_SET( bank );
|
|
write_page_snes( 0, addrH, buff, snes_rom_wr, snes_rom_rd );
|
|
}
|
|
case SNESRAM:
|
|
//warn addrX = ((buff->page_num)>>8);
|
|
break;
|
|
default:
|
|
return ERR_BUFF_UNSUP_MEM_TYPE;
|
|
}
|
|
|
|
|
|
return SUCCESS;
|
|
}
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