422 lines
11 KiB
C
422 lines
11 KiB
C
#ifndef _pinport_al_h
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#define _pinport_al_h
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//Define the board type in makefile
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//#define AVR_KAZZO
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//#define STM_ADAPTER
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//#define STM_INL6
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#ifdef AVR_CORE
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#include "avr_gpio.h"
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#elif STM_CORE
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#include <stm32f0xx.h>
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#endif
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//=============================================================================================
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//
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// PINPORT ABSTRACTION LAYER
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//
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//=============================================================================================
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//
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// The pinport abstraction layer creates definitions of generic device GPIO ports.
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// These generic ports are designed to make high level firmware generic to the
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// actual underlying hardware. The ports created have defined sizes and access rules
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// that keeps firmware from growing in complexity based on the specific hardware.
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//
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// Idea is to define ports which are available on all hardware, but also create ports
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// which may not be available to other hardwares. If the firmware is instructed to
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// perform an operation on a port that's not present, or not initialized/setup error
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// codes will be sent back to the host to designate the lack of port presence.
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//
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// ---------------------------------------------------------------------------------------
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// CONTROL PORT: 16bits for function
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// C15-0
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// Directionality: All pins are able to be toggled between input/output individually
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// Driver: All pins indiv selectable pull-up or float for input. Output always push pull.
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// Write/Output: Bit access only, no byte/word accesses
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// Read/Input: Bit access only, returned byte/word will be zero if clear, non-zero if set
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// ---------------------------------------------------------------------------------------
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// STM32 GPIO registers are quite different than AVR style
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// they are more flexible/capable, but a little tricky to interface with
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// some features present on STM32 pins, but not AVR
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// - PULL-DOWN ability (and PULL-UP like AVR)
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// - Speed/Slew rate selection
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// - Open drain outputs (and push/pull like AVR)
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// - Bit set/reset registers to remove necessity of RMW operations
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// - Lockability to keep port config bits from changing until reset
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// - GPIO blocks must be provided a clock and enabled to "turn on"
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// failing to do so will cause hard faults when accessing registers!!
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//
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// All GPIO registers can be accessed in byte, halfword, or 32bit full words
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// unless otherwise noted
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//
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// GPIOx->MODER[1:0] 32bit registers control direction/type of driver
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// 00- Input (default reset state, except SWC-PA15 & SWD-PA13 default AF)
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// 01- Gen Purp Output
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// 10- Alternate func (SPI, I2C, etc)
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// 11- reserved
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// MODER[1] typically leave clear unless using AltFunc
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// MODER[0] becomes equivalent of AVR DDR
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#define MODER_OP 0x01
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#define MODER_AF 0x10
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//
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// GPIOx->OTYPER 16bit registers control driver type
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// 0- Push Pull (default reset state)
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// 1- Open Drain
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use pushpull as AVR does
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//
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// GPIOx->OSPEEDR[1:0] 32bit registers control pin driver speed/slew
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// x0- Low speed (default reset state, except SWD-PA13 default High Spd)
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// 01- Medium speed
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// 11- High speed
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use slow speed
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//
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// GPIOx->PUPDR[1:0] 32bit registers control pull-up/down resistors
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// this register is in effect even when alternate functions are enabled
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// 00- floating/disabled, no pull-up/down (default for most pins except below)
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// 01- Pull-up enabled (default SWD-PA13) also CIRAM A10
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// 10- Pull-down enabled (default SWC-PA14)
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// 11- Reserved, don't use (prob enables both which would be bad...)
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// PUPDR[0] is kinda like AVR PORT when DDR is set to INPUT, and PUPDR[1]=0
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// This ends up being a little cleaner than AVR i/o interfacing
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// Can probably just enable pull-ups on everything and leave it like that
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// -only exception being USB pins (PA11/12) better leave those floating
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#define PUPDR_FLT 0x00
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#define PUPDR_PU 0x01
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#define PUPDR_PD 0x10
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//
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// GPIOx->IDR 16bit register used to read current input level on pin
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// this register is read only
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//
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// GPIOx->ODR 16bit register used to set output of pin if enabled by MODER
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// this register is read/writeable
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//
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// GPIOx->BSRR 32bit register to only set/clear pins
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// BR[31:16] upper halfword is will reset/clear pin if written to '1' value
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// BS[15:00] lower halfword is will set pin if written to '1' value
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// writing 0 to any bit has no effect
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// if setting both BS register has priority (bit will be set)
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// this register is write only!
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//
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// GPIO->BRR 16bit register equivalent to upper word of BSRR register above
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// provides convinent separate BR register that doesn't need shifted
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//
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// GPIOx->LCKR 17bit register MUST BE ACCESSED in 32bit full words!!!
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// complex sequence needed to set, but once done lock config/altfunc
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// bits for that GPIO. I interpret this to mean the registers above
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// plus AF registers, exception of IDR, ODR, BSRR registers
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// Good to use this for things than we don't want to accidentally change:
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// - USB & XTAL pins come to mind as good candidates
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//
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// GPIOx->AFRL/H 2 sets of 32bit registers to determine alternate function
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// of GPIO if enabled with MODER registers. Default is AF0 at reset
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// AVR GPIO are rather simple in comparison to STM32 GPIO:
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//
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// DDRx 8bit direction register
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// Determines 'direction' of pin driver
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// set for output, clear of input
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// reads give current status of register
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//
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// PORTx 8bit output/pullup register
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// writes set/clear pin if DDR is set/OP
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// write '1' to enable pull-up if DDR is clear/IP
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// write '0' to disable pull-up if DDR is clear/IP
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// reads give current status of register
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// bit access must be done by means of RMW/shadow reg
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//
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// PINx 8bit read register
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// read when DDR is clear/IP to get current pin level
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// reading when O/P is of little use, as should be value of PORTx
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// read only register
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//kaz6 is PB1
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//#define LED (1U)
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//#define IOP_LED_EN RCC_AHBENR_GPIOBEN
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//#define GPIO_LED GPIOB
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//
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////kaz adapter is PC13
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//#define LED (13U)
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//#define IOP_LED_EN RCC_AHBENR_GPIOCEN
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//#define GPIO_LED GPIOC
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//
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////kaz adapter data0 debug is PB8
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//#define DEBUG (8U)
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//#define IOP_DEBUG_EN RCC_AHBENR_GPIOBEN
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//#define GPIO_DEBUG GPIOB
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//
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//#define LED_ON() (GPIO_LED->ODR |= (0x1U<<LED))
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//#define LED_OFF() (GPIO_LED->ODR &= ~(0x1U<<LED))
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//
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//#define DEBUG_HI() (GPIO_DEBUG->ODR |= (0x1U<<DEBUG))
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//#define DEBUG_LO() (GPIO_DEBUG->ODR &= ~(0x1U<<DEBUG))
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#ifdef STM_INL6
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#define IOP_LED_EN RCC_AHBENR_GPIOBEN
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//C0 "ROMSEL" pinA0
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#define C0bank GPIOA
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#define C0 (0U)
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//C1 "R/W" pinA1
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#define C1bank GPIOA
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#define C1 (1U)
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//C2 "/RD" pinA2
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#define C2bank GPIOA
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#define C2 (2U)
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//C3 "/WR" pinA3
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#define C3bank GPIOA
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#define C3 (3U)
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//C4 "AUDIO_L" pinA4
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#define C4bank GPIOA
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#define C4 (4U)
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//C5 "AUDIO_R" pinA5
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#define C5bank GPIOA
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#define C5 (5U)
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//C6 "CART_RST" pinA6
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#define C6bank GPIOA
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#define C6 (6U)
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//C7 "KEY_DIN" pinA7
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#define C7bank GPIOA
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#define C7 (7U)
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//C8 "CLK_OUT" pinA8
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#define C8bank GPIOA
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#define C8 (8U)
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//C9 "FLIPFLOP" pinB0
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#define C9bank GPIOB
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#define C9 (0U)
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//C10 "LED" pinB1
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#define C10bank GPIOB
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#define C10 (1U)
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//C11 "KEY_DOUT" pinD2
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#define C11bank GPIOD
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#define C11 (2U)
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//C12 "BOOTLOAD" not present
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//#define C12bank GPIO
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//#define C12 (U)
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//C13 "SWDIO" pinA13
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#define C13bank GPIOA
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#define C13 (13U)
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//C14 "SWCLK" pinA14
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#define C14bank GPIOA
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#define C14 (14U)
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//C15 "IRQ" pinA15
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#define C15bank GPIOA
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#define C15 (15U)
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#endif
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#ifdef STM_ADAPTER
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#define IOP_LED_EN RCC_AHBENR_GPIOCEN
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//C0 "ROMSEL" pinA4
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#define C0bank GPIOA
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#define C0 (4U)
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//C1 "R/W" pinA5
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#define C1bank GPIOA
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#define C1 (5U)
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//C2 "/RD" pinA7
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#define C2bank GPIOA
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#define C2 (7U)
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//C3 "/WR" pinB0
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#define C3bank GPIOB
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#define C3 (0U)
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//C4 "AUDIO_L/AHL" pinB1
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#define C4bank GPIOB
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#define C4 (1U)
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//C5 "AUDIO_R/FREE" pinA6
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#define C5bank GPIOA
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#define C5 (6U)
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//C6 "CART_RST/EXP0" pinA0
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#define C6bank GPIOA
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#define C6 (0U)
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////C7 "KEY_DIN" pinA7
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//#define C7bank GPIOA
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//#define C7 (7U)
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//C8 "CLK_OUT/M2" pinA3
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#define C8bank GPIOA
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#define C8 (3U)
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//C9 "FLIPFLOP/AXL" pinA2
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#define C9bank GPIOA
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#define C9 (2U)
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//C10 "LED" pinC13
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#define C10bank GPIOC
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#define C10 (13U)
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//C11 "KEY_DOUT/CIRAMCE" pinA10
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#define C11bank GPIOA
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#define C11 (10U)
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//C12 "BOOTLOAD" not present
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//#define C12bank GPIO
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//#define C12 (U)
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//C13 "SWDIO/CIRAMA10" pinA13
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#define C13bank GPIOA
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#define C13 (13U)
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//C14 "SWCLK" pinA14
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#define C14bank GPIOA
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#define C14 (14U)
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//C15 "IRQ" pinA15
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#define C15bank GPIOA
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#define C15 (15U)
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#endif
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#ifdef AVR_KAZZO
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//C0 "ROMSEL" pinC1
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#define C0bank GPIOC
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#define C0 (1U)
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//C1 "R/W" pinC2
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#define C1bank GPIOC
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#define C1 (2U)
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//C2 "/RD" pinC4
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#define C2bank GPIOC
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#define C2 (4U)
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//C3 "/WR" pinC5
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#define C3bank GPIOC
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#define C3 (5U)
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//C4 "AUDIO_L/AHL" pinC7
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#define C4bank GPIOC
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#define C4 (7U)
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//C5 "AUDIO_R/FREE" pinC3
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#define C5bank GPIOC
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#define C5 (3U)
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//C6 "CART_RST/EXP0" pinD0
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#define C6bank GPIOD
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#define C6 (0U)
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////C7 "KEY_DIN" pinA7
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//#define C7bank GPIOA
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//#define C7 (7U)
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//C8 "CLK_OUT/M2" pinC0
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#define C8bank GPIOC
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#define C8 (0U)
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//C9 "FLIPFLOP/AXL" pinD7
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#define C9bank GPIOD
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#define C9 (7U)
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//C10 "LED" pinD1
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#define C10bank GPIOD
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#define C10 (1U)
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//C11 "KEY_DOUT/CIRAMCE" pinC6
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#define C11bank GPIOC
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#define C11 (6U)
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//C12 "BOOTLOAD" pinD6
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#define C12bank GPIOD
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#define C12 (6U)
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//C13 "SWDIO/CIRAMA10" pinD5
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#define C13bank GPIOD
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#define C13 (5U)
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////C14 "SWCLK" pinA14
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//#define C14bank GPIOA
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//#define C14 (14U)
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//C15 "IRQ" pinD3
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#define C15bank GPIOD
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#define C15 (3U)
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#endif
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//pinport abstraction layer pin mappings roughly based on inl6 schematic
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//C0 "ROMSEL"
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//C1 "R/W"
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//C2 "/RD"
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//C3 "/WR"
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//C4 "AUDIO_L"
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//C5 "AUDIO_R"
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//C6 "CART_RST"
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//C7 "KEY_DIN"
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//C8 "CLK_OUT"
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//C9 "FLIPFLOP"
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//C10 "LED"
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//C11 "KEY_DOUT"
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//C12 "BOOTLOAD"
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//C13 "SWDIO"
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//C14 "SWCLK"
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//C15 "IRQ"
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#define LED C10
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#define LEDbank C10bank
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#ifdef STM_CORE
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// 00- Input (default reset state, except SWC-PA15 & SWD-PA13 default AF)
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// 01- Gen Purp Output
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// Assume MODER[1] is clear (default setting, only gets set of AF)
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// Assume PUPDR[1] is clear (default setting, only set if pulldown enabled)
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#define PCb_IP_PU(bank, pin) bank->MODER &= ~(MODER_OP<<(pin*2)); bank->PUPDR |= (PUPDR_PU<<(pin*2))
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#define PCb_IP_FLT(bank, pin) bank->MODER &= ~(MODER_OP<<(pin*2)); bank->PUPDR &= ~(PUPDR_PU<<(pin*2))
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#define PCb_OP_EN(bank, pin) bank->MODER |= (MODER_OP<<(pin*2))
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#define PCb_READ(bank, pin, val) val = (bank->IDR & (1<<pin))
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#define PCb_SET_HI(bank, pin) bank->BSRR = 1<<pin
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// PCb_SET_HI(C0bank, C0)
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#define PCb_SET_LO(bank, pin) bank->BRR = 1<<pin
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#endif //STM_CORE
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#ifdef AVR_CORE
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#define PCb_IP_PU(bank, pin) bank->DDR &= ~(1<<pin); bank->PORT |= (1<<pin)
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#define PCb_IP_FLT(bank, pin) bank->DDR &= ~(1<<pin); bank->PORT &= ~(1<<pin)
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#define PCb_OP_EN(bank, pin) bank->DDR |= (1<<pin)
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#define PCb_READ(bank, pin, val) val = (bank->PIN & (1<<pin))
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#define PCb_SET_HI(bank, pin) bank->PORT |= (1<<pin)
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#define PCb_SET_LO(bank, pin) bank->PORT &= ~(1<<pin)
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#endif //AVR_CORE
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#endif
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