741 lines
19 KiB
C
741 lines
19 KiB
C
#ifndef _pinport_al_h
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#define _pinport_al_h
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//Define the board type in makefile
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//#define AVR_KAZZO
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//#define STM_ADAPTER
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//#define STM_INL6
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#ifdef AVR_CORE
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#include "avr_gpio.h"
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#elif STM_CORE
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#include <stm32f0xx.h>
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#endif
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//=============================================================================================
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//
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// PINPORT ABSTRACTION LAYER
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//
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//=============================================================================================
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//
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// The pinport abstraction layer creates definitions of generic device GPIO ports.
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// These generic ports are designed to make high level firmware generic to the
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// actual underlying hardware. The ports created have defined sizes and access rules
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// that keeps firmware from growing in complexity based on the specific hardware.
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//
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// Idea is to define ports which are available on all hardware, but also create ports
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// which may not be available to other hardwares. If the firmware is instructed to
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// perform an operation on a port that's not present, or not initialized/setup error
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// codes will be sent back to the host to designate the lack of port presence.
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//
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// STM32 GPIO registers are quite different than AVR style
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// they are more flexible/capable, but a little tricky to interface with
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// some features present on STM32 pins, but not AVR
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// - PULL-DOWN ability (and PULL-UP like AVR)
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// - Speed/Slew rate selection
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// - Open drain outputs (and push/pull like AVR)
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// - Bit set/reset registers to remove necessity of RMW operations
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// - Lockability to keep port config bits from changing until reset
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// - GPIO blocks must be provided a clock and enabled to "turn on"
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// failing to do so will cause hard faults when accessing registers!!
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//
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// All GPIO registers can be accessed in byte, halfword, or 32bit full words
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// unless otherwise noted
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//
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// GPIOx->MODER[1:0] 32bit registers control direction/type of driver
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// 00- Input (default reset state, except SWC-PA15 & SWD-PA13 default AF)
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// 01- Gen Purp Output
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// 10- Alternate func (SPI, I2C, etc)
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// 11- reserved
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// MODER[1] typically leave clear unless using AltFunc
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// MODER[0] becomes equivalent of AVR DDR
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#define MODER_OP 0x01
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#define MODER_OP_ALL 0x55555555
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#define MODER_AF 0x10
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//
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// GPIOx->OTYPER 16bit registers control driver type
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// 0- Push Pull (default reset state)
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// 1- Open Drain
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use pushpull as AVR does
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//
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// GPIOx->OSPEEDR[1:0] 32bit registers control pin driver speed/slew
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// x0- Low speed (default reset state, except SWD-PA13 default High Spd)
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// 01- Medium speed
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// 11- High speed
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use slow speed
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//
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// GPIOx->PUPDR[1:0] 32bit registers control pull-up/down resistors
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// this register is in effect even when alternate functions are enabled
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// 00- floating/disabled, no pull-up/down (default for most pins except below)
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// 01- Pull-up enabled (default SWD-PA13) also CIRAM A10
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// 10- Pull-down enabled (default SWC-PA14)
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// 11- Reserved, don't use (prob enables both which would be bad...)
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// PUPDR[0] is kinda like AVR PORT when DDR is set to INPUT, and PUPDR[1]=0
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// This ends up being a little cleaner than AVR i/o interfacing
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// Can probably just enable pull-ups on everything and leave it like that
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// -only exception being USB pins (PA11/12) better leave those floating
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//#define PUPDR_FLT 0x00
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#define PUPDR_PU 0x01
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#define PUPDR_PD 0x10
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//
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// GPIOx->IDR 16bit register used to read current input level on pin
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// this register is read only
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//
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// GPIOx->ODR 16bit register used to set output of pin if enabled by MODER
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// this register is read/writeable
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//
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// GPIOx->BSRR 32bit register to only set/clear pins
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// BR[31:16] upper halfword is will reset/clear pin if written to '1' value
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// BS[15:00] lower halfword is will set pin if written to '1' value
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// writing 0 to any bit has no effect
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// if setting both BS register has priority (bit will be set)
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// this register is write only!
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//
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// GPIO->BRR 16bit register equivalent to upper word of BSRR register above
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// provides convinent separate BR register that doesn't need shifted
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//
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// GPIOx->LCKR 17bit register MUST BE ACCESSED in 32bit full words!!!
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// complex sequence needed to set, but once done lock config/altfunc
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// bits for that GPIO. I interpret this to mean the registers above
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// plus AF registers, exception of IDR, ODR, BSRR registers
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// Good to use this for things than we don't want to accidentally change:
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// - USB & XTAL pins come to mind as good candidates
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//
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// GPIOx->AFRL/H 2 sets of 32bit registers to determine alternate function
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// of GPIO if enabled with MODER registers. Default is AF0 at reset
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// AVR GPIO are rather simple in comparison to STM32 GPIO:
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//
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// DDRx 8bit direction register
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// Determines 'direction' of pin driver
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// set for output, clear of input
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// reads give current status of register
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//
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// PORTx 8bit output/pullup register
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// writes set/clear pin if DDR is set/OP
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// write '1' to enable pull-up if DDR is clear/IP
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// write '0' to disable pull-up if DDR is clear/IP
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// reads give current status of register
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// bit access must be done by means of RMW/shadow reg
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//
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// PINx 8bit read register
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// read when DDR is clear/IP to get current pin level
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// reading when O/P is of little use, as should be value of PORTx
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// read only register
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// ---------------------------------------------------------------------------------------
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// CONTROL PORT
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//
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// This port is present on all devices, however not all pins are present depending on device
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// Keeping this port as bit access only makes it so there is no limit to number of pins.
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// Directionality: All pins are able to be toggled between input/output individually
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// Driver: All pins indiv selectable pull-up or float for input. Output always push pull.
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// Write/Output: Bit access only, no byte/word accesses
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// Read/Input: Bit access only, returned byte/word will be zero if clear, non-zero if set
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//
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// PORT C pin definitions
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// Don't assign one mcu pin to more than one pin in this port!
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// mcu pin can be assigned in other ports, as initializing
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// those ports will 'disable' the pin in this port.
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// if the pin has multiple purposes and would like to give
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// it different names based on the cart inserted, just create
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// multiple defines/names for the one PCn pin.
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//
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// ---------------------------------------------------------------------------------------
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#ifdef STM_INL6
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// PC0 "MCO" mcupinA8
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#define C0bank GPIOA
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#define C0 (8U)
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// PC1 "ROMSEL" mcupinA0
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#define C1bank GPIOA
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#define C1 (0U)
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// PC2 "PRGRW" mcupinA1
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#define C2bank GPIOA
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#define C2 (1U)
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// PC3 "PAXL"
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// Not defined
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// PC4 "CSRD" mcupinA2
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#define C4bank GPIOA
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#define C4 (2U)
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// PC5 "CSWR" mcupinA3
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#define C5bank GPIOA
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#define C5 (3U)
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// PC6 "CICE" mcupinA10
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#define C6bank GPIOA
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#define C6 (10U)
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// PC7 "AHL"
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// Not defined
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// PC8 "EXP0" mcupinA6
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#define C8bank GPIOA
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#define C8 (6U)
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// PC9 "LED" mcupinB1
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#define C9bank GPIOB
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#define C9 (1U)
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// PC10 "IRQ" mcupinA15
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#define C10bank GPIOA
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#define C10 (15U)
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// PC11 "CIA10" mcupinA9
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#define C11bank GPIOA
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#define C11 (9U)
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// PC12 "BL"
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// Not defined
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// PC13 "AXL"
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// Not defined
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// PC14 "AUDL" mcupinA4
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#define C14bank GPIOA
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#define C14 (4U)
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// PC15 "AUDR" mcupinA5
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#define C15bank GPIOA
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#define C15 (5U)
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// PC16 "CIN" mcupinA7
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#define C16bank GPIOA
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#define C16 (7U)
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// PC17 "SWD" mcupinA13
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#define C17bank GPIOA
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#define C17 (13U)
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// PC18 "SWC" mcupinA14
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#define C18bank GPIOA
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#define C18 (14U)
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// PC19 "AFL" mcupinB0
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#define C19bank GPIOB
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#define C19 (0U)
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// PC20 "COUT" mcupinD2
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#define C20bank GPIOD
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#define C20 (2U)
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/* NEED MORE UNIQUE names for these pins to not conflict with Data port definitions...
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// PC21 "D8" mcupinB10
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#define C21bank GPIOB
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#define C21 (10U)
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// PC22 "D9" mcupinB11
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#define C22bank GPIOB
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#define C22 (11U)
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// PC23 "D10" mcupinB12
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#define C23bank GPIOB
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#define C23 (12U)
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// PC24 "D11" mcupinB13
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#define C24bank GPIOB
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#define C24 (13U)
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// PC25 "D12" mcupinB14
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#define C25bank GPIOB
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#define C25 (14U)
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// PC26 "D13" mcupinB15
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#define C26bank GPIOB
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#define C26 (15U)
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*/
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#define IOP_LED_EN RCC_AHBENR_GPIOBEN
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#endif //STM_INL6
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#ifdef STM_ADAPTER
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// PC0 "MCO" mcupinA3
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#define C0bank GPIOA
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#define C0 (3U)
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// PC1 "ROMSEL" mcupinA4
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#define C1bank GPIOA
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#define C1 (4U)
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// PC2 "PRGRW" mcupinA5
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#define C2bank GPIOA
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#define C2 (5U)
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// PC3 "PAXL"
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// Not defined
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// PC4 "CSRD" mcupinA7
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#define C4bank GPIOA
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#define C4 (7U)
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// PC5 "CSWR" mcupinB0
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#define C5bank GPIOB
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#define C5 (0U)
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// PC6 "CICE" mcupinA10
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#define C6bank GPIOA
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#define C6 (10U)
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// PC7 "AHL" mcupinB1
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#define C7bank GPIOB
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#define C7 (1U)
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// PC8 "EXP0" mcupinA0
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#define C8bank GPIOA
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#define C8 (0U)
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// PC9 "LED" mcupinC13
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#define C9bank GPIOC
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#define C9 (13U)
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// PC10 "IRQ" mcupinA15
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#define C10bank GPIOA
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#define C10 (15U)
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// PC11 "CIA10" mcupinA13
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#define C11bank GPIOA
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#define C11 (13U)
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// PC12 "BL"
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// Not defined
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// PC13 "AXL" mcupinA2
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#define C13bank GPIOA
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#define C13 (2U)
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// PC14 "AUDL"
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// Not defined
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// PC15 "AUDR"
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// Not defined
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// PC16 "CIN"
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// Not defined
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// PC17 "SWD" mcupinA13
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// Not defined due to shared with CIRAM A10
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// PC18 "SWC" mcupinA14
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#define C18bank GPIOA
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#define C18 (14U)
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// PC19 "AFL"
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// Not defined
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// PC20 "COUT"
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// Not defined
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// PC21 "D8"
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// Not defined
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// PC22 "D9"
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// Not defined
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// PC23 "D10"
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// Not defined
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// PC24 "D11"
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// Not defined
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// PC25 "D12"
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// Not defined
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// PC26 "D13"
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// Not defined
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#define IOP_LED_EN RCC_AHBENR_GPIOCEN
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#endif //STM_ADAPTER
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#ifdef AVR_KAZZO
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// PC0 "MCO" mcupinC0
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#define C0bank GPIOC
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#define C0 (0U)
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// PC1 "ROMSEL" mcupinC1
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#define C1bank GPIOC
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#define C1 (1U)
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// PC2 "PRGRW" mcupinC2
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#define C2bank GPIOC
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#define C2 (2U)
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// PC3 "PAXL" mcupinC3
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// Not defined
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// PC4 "CSRD" mcupinC4
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#define C4bank GPIOC
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#define C4 (4U)
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// PC5 "CSWR" mcupinC5
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#define C5bank GPIOC
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#define C5 (5U)
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// PC6 "CICE" mcupinC6
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#define C6bank GPIOC
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#define C6 (6U)
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// PC7 "AHL" mcupinC7
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#define C7bank GPIOC
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#define C7 (7U)
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// PC8 "EXP0" mcupinD0
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#define C8bank GPIOD
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#define C8 (0U)
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// PC9 "LED" mcupinD1
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#define C9bank GPIOD
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#define C9 (1U)
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// PC10 "IRQ" mcupinD3
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#define C10bank GPIOD
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#define C10 (3U)
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// PC11 "CIA10" mcupinD5
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#define C11bank GPIOD
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#define C11 (5U)
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// PC12 "BL" mcupinD6
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#define C12bank GPIOD
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#define C12 (6U)
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// PC13 "AXL" mcupinD7
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#define C13bank GPIOD
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#define C13 (7U)
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// PC14 "AUDL"
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// not defined
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// PC15 "AUDR"
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// not defined
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// PC16 "CIN"
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// not defined
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// PC17 "SWD"
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// not defined
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// PC18 "SWC"
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// not defined
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// PC19 "AFL"
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// not defined
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// PC20 "COUT"
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// not defined
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// PC21 "D8"
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// not defined
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// PC22 "D9"
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// not defined
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// PC23 "D10"
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// not defined
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// PC24 "D11"
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// not defined
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// PC25 "D12"
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// not defined
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// PC26 "D13"
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// not defined
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#endif //AVR_KAZZO
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////////////////////////////////////////////////////////////////////////////////
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// PORT C pin mappings
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////////////////////////////////////////////////////////////////////////////////
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//
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// PC0-13 are defined based on majority of avr kazzos PORTC-PORTD
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// PC0 "MCO" mcu clock out M2/phi2, Sysclk, etc
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#define MCO C0
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#define MCObank C0bank
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#define M2 C0
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#define M2bank C0bank
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// PC1 "ROMSEL" Cartridge rom enable
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#define ROMSEL C1
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#define ROMSELbank C1bank
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// PC2 "PRGRW" NES CPU R/W signal
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#define PRGRW C2
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#define PRGRWbank C2bank
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// PC3 "PAXL" purple kazzo EXP flipflop latch, FREE on most kazzos
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#define PAXL C3
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#define PAXLbank C3bank
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// PC4 "CSRD" NES CHR/SNES /RD
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#define CSRD C4
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#define CSRDbank C4bank
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// PC5 "CSWR" NES CHR/SNES /WR
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#define CSWR C5
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#define CSWRbank C5bank
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// PC6 "CICE" NES CIRAM /CE
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#define CICE C6
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#define CICEbank C6bank
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// PC7 "AHL" ADDR HI Latch
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#define AHL C7
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#define AHLbank C7bank
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// PC8 "EXP0" NES EXP0, cart-console /RESET
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#define EXP0 C8
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#define EXP0bank C8bank
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// PC9 "LED" kazzos tied this to NES EXP9, INL6 connects to CIC CLK
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#define LED C9
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#define LEDbank C9bank
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// PC10 "IRQ" console CPU interrupt from cart
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#define IRQ C10
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#define IRQbank C10bank
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// PC11 "CIA10" NES CIRAM A10
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#define CIA10 C11
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#define CIA10bank C11bank
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// PC12 "BL" Bootloader pin
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#define BL C12
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#define BLbank C12bank
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// PC13 "AXL" EXP FF latch and /OE, purple kazzos this was only /OE
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#define AXL C13
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#define AXLbank C13bank
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// INLretro6 adds following pins
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// PC14 "AUDL" cart audio
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#define AUDL C14
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#define AUDLbank C14bank
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// PC15 "AUDR" cart audio
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#define AUDR C15
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#define AUDRbank C15bank
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// PC16 "CIN" CIC data in
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#define CIN C16
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#define CINbank C16bank
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// PC17 "SWD" mcu debug
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#define SWD C17
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#define SWDbank C17bank
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// PC18 "SWC" mcu debug
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#define SWC C18
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#define SWCbank C18bank
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// PC19 "AFL" flipflop addr expansion for FF0-7
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#define AFL C19
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#define AFLbank C19bank
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// PC20 "COUT" CIC data out
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#define COUT C20
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#define COUTbank C20bank
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// INLretro6 gains direct control over NES EXP port and is used for N64 control pins:
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/*
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// PC21 "D8"
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#define D8 C21
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#define D8bank C21bank
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// PC22 "D9"
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#define D9 C22
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#define D9bank C22bank
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// PC23 "D10"
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#define D10 C23
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#define D10bank C23bank
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// PC24 "D11"
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#define D11 C24
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#define D11bank C24bank
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// PC25 "D12"
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#define D12 C25
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#define D12bank C25bank
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// PC26 "D13"
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#define D12 C26
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#define D12bank C26bank
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// PC27 "D14"
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#define D12 C27
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#define D12bank C27bank
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// D15 & D16 are defined as CICE/CIA10 above
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*/
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#ifdef STM_CORE
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#define CTL_IP_PU(bank, pin) bank->MODER &= ~(MODER_OP<<(pin*2)); bank->PUPDR |= (PUPDR_PU<<(pin*2))
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#define CTL_IP_FLT(bank, pin) bank->MODER &= ~(MODER_OP<<(pin*2)); bank->PUPDR &= ~(PUPDR_PU<<(pin*2))
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#define CTL_OP(bank, pin) bank->MODER |= (MODER_OP<<(pin*2))
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#define CTL_READ(bank, pin, val) val = (bank->IDR & (1<<pin))
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#define CTL_SET_HI(bank, pin) bank->BSRR = 1<<pin
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#define CTL_SET_LO(bank, pin) bank->BRR = 1<<pin
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#endif //STM_CORE
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#ifdef AVR_CORE
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#define CTL_IP_PU(bank, pin) bank->DDR &= ~(1<<pin); bank->PORT |= (1<<pin)
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#define CTL_IP_FLT(bank, pin) bank->DDR &= ~(1<<pin); bank->PORT &= ~(1<<pin)
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#define CTL_OP(bank, pin) bank->DDR |= (1<<pin)
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#define CTL_READ(bank, pin, val) val = (bank->PIN & (1<<pin))
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#define CTL_SET_HI(bank, pin) bank->PORT |= (1<<pin)
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#define CTL_SET_LO(bank, pin) bank->PORT &= ~(1<<pin)
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#endif //AVR_CORE
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// CONTROL PORT MACROS to simplify flipflop operations
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//
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#define _AHL_CLK() CTL_SET_HI(AHLbank, AHL); CTL_SET_LO(AHLbank, AHL)
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#define _AXL_CLK() CTL_SET_HI(AXLbank, AXL); CTL_SET_LO(AXLbank, AXL)
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// ---------------------------------------------------------------------------------------
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// DATA PORT 8bit
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//
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// This port is present on all devices
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// Directionality: All pins are bidirectional controlled as a whole
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// Driver: All pins are push-pull, and unknown floating/pull-up when input
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// main reason to be unknown is AVR uses PORT for pull-up enable
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// don't want to require re-enabling pullups for every data access
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// Write/Output: Byte access only, no bit accesses. Must be returned to input after read!
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// Read/Input: Default condition, byte access only
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//
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// ---------------------------------------------------------------------------------------
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//
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#ifdef STM_INL6
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//All 8bits are on GPIOB inorder, but mapped to bits9-2 for 5v tolerance
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//I get why I designed it that way so D8-13 could follow in order..
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//But with D8-15 required to be broken up anyways, perhaps it would have
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//made more sense to map D0-7 to bits 9-15 so byte access could be performed
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//without shifting on Data7-0...
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//IDK if I will reroute the board for production or not... Only other way to
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//do it senisbly really makes a mess of the upper byte of Data
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#define Dbank GPIOB
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//IP and OP assume MODER[1] is clear (ie not set to Alt Func)
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#define _DATA_IP() Dbank->MODER &= ~(MODER_OP_ALL & 0x000FFFF0)
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#define _DATA_OP() Dbank->MODER |= (MODER_OP_ALL & 0x000FFFF0)
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#define _DATA_SET(data) Dbank->ODR = (Dbank->ODR & 0xFC03) | (data<<2)
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#define _DATA_RD(data) data = (Dbank->IDR>>2) & 0x00FF
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#endif //STM_INL6
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#ifdef STM_ADAPTER
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//All 8bits are on GPIOB inorder, but mapped to bits15-8
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#define Dbank GPIOB
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//IP and OP assume MODER[1] is clear (ie not set to Alt Func)
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#define _DATA_IP() Dbank->MODER &= ~(MODER_OP_ALL & 0xFFFF0000)
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#define _DATA_OP() Dbank->MODER |= (MODER_OP_ALL & 0xFFFF0000)
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//TODO create byte wide port structs to grant byte accesses so doesn't need shifted
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#define _DATA_SET(data) Dbank->ODR = (Dbank->ODR & 0x00FF) | (data<<8)
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#define _DATA_RD(data) data = (Dbank->IDR>>8) & 0x00FF
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#endif //STM_ADAPTER
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#ifdef AVR_KAZZO
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//All 8bits are on GPIOB aligned perfectly
|
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#define Dbank GPIOB
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#define _DATA_IP() Dbank->DDR = 0x00
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#define _DATA_OP() Dbank->DDR = 0xFF
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#define _DATA_SET(data) Dbank->PORT = data
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#define _DATA_RD(data) data = Dbank->PIN
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#endif //AVR_KAZZO
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// ---------------------------------------------------------------------------------------
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|
// ADDRESS PORT 16bit
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|
//
|
|
// This port is present on all devices
|
|
// Directionality: All pins are forced output
|
|
// Driver: All pins are push-pull
|
|
// Write/Output: Byte/half word access only, no bit accesses
|
|
// Read/Input: Not supported
|
|
//
|
|
// ---------------------------------------------------------------------------------------
|
|
|
|
#ifdef STM_INL6
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|
|
|
//All 16bits are on GPIOC in perfect alignment
|
|
#define Abank GPIOC
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|
|
|
#define _ADDR_IP() Abank->MODER &= ~MODER_OP_ALL
|
|
#define _ADDR_OP() Abank->MODER |= MODER_OP_ALL
|
|
#define _ADDRL(low) Abank->ODR = (Abank->ODR & 0xFF00) | low
|
|
#define _ADDRH(high) Abank->ODR = (Abank->ODR & 0x00FF) | (high<<8)
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|
#define _ADDR(hword) Abank->ODR = hword
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|
|
#endif //STM_INL6
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|
|
#ifdef STM_ADAPTER
|
|
|
|
// A15-8 are behind AHL flipflop
|
|
// A7-6 are on GPIO A9-8
|
|
// A5-0 are on GPIO A7-2
|
|
#define A76bank GPIOA
|
|
#define A50bank GPIOB
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|
|
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#define _ADDR_IP() A76bank->MODER &= ~(MODER_OP_ALL & 0x000F0000); A50bank->MODER &= ~(MODER_OP_ALL & 0x0000FFF0)
|
|
#define _ADDR_OP() A76bank->MODER |= (MODER_OP_ALL & 0x000F0000); A50bank->MODER |= (MODER_OP_ALL & 0x0000FFF0)
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|
#define _ADDRL(low) A76bank->ODR = (A76bank->ODR & 0xFCFF) | ((low & 0xC0)<<2);A50bank->ODR = (A50bank->ODR & 0xFF03) | ((low & 0x3F)<<2)
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|
//clocks must be initialized, Data bus clear
|
|
#define _ADDRH(high) _DATA_OP(); _DATA_SET(high); _AHL_CLK(); _DATA_IP();
|
|
#define _ADDR(hword) ADDRL(hword); _ADDRH(hword>>8)
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|
|
|
#endif //STM_ADAPTER
|
|
|
|
#ifdef AVR_KAZZO
|
|
|
|
// A15-8 are behind AHL flipflop
|
|
// A7-0 are on GPIOA perfectly aligned
|
|
#define _ALbank GPIOA
|
|
|
|
#define _ADDRL(low) GPIOA->PORT = low
|
|
//clocks must be initialized, Data bus clear
|
|
#define _ADDRH(high) _DATA_OP(); _DATA_SET(high); _AHL_CLK(); _DATA_IP();
|
|
#define _ADDR(hword) ADDRL(hword); _ADDRH(hword>>8)
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|
|
|
#endif //AVR_KAZZO
|
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|
|
#endif
|