582 lines
23 KiB
C
582 lines
23 KiB
C
#ifndef _pinport_h
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#define _pinport_h
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#include "logic.h"
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#include "shared_errors.h"
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#include "shared_dict_pinport.h"
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uint8_t pinport_opcode_only( uint8_t opcode );
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uint8_t pinport_opcode_8b_operand( uint8_t opcode, uint8_t operand );
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uint8_t pinport_opcode_16b_operand( uint8_t opcode, uint8_t operandMSB, uint8_t operandLSB );
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uint8_t pinport_opcode_24b_operand( uint8_t opcode, uint8_t operandMSB, uint8_t operandMID, uint8_t operandLSB );
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uint8_t pinport_opcode_8b_return( uint8_t opcode, uint8_t *rvalue );
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void software_AHL_CLK();
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void software_AXL_CLK();
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//This file contains pinout translations from AVR names to "kazzo" names
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//this file also works to make all kazzo versions compatible and "alike"
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//There are defines for kazzo version, turns out unique early versions
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//can be differentiated by solder mask color.
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//Final version is default and doesn't need any defines
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//#define PURPLE_KAZZO
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//#define GREEN_KAZZO
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//=======================================================
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//History of PCB revsisions produced by InfiniteNesLives
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//=======================================================
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//
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// uncomment define if buiding for either of the first two versions
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//#define PURPLE_KAZZO
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// First printed circuit board version
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// only handful made (less than 10?)
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// Purple solder mask
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// Labeled "Kazzo PCB rev 3.0"
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// Dated 8/22/2011
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// * Only contained NES and Famicom connectors
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// * Had bug where USB data lines mixed up
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// -manually fixed during component assembly
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// * Naruko determined this should have still been v1 board
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// -due to it's overall design and conflicting with someother v3 board
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// * This was my first ever PCB design and one of the first
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// times designing something for the NES/FC. Looking
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// back at the design there were some very noob decisions...
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// * INPUT/OUTPUT differences:
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// EXP9 - PD1/LED jumper
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// when closed, PD1 controls NES EXP9 and LED
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// when open, EXP9 is floating PD1 only controls LED
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// NES EXP9 was connected to GND pin #16 on FC
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// -I must have thought that GND pin could serve
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// different purpose..
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// -Result is PD1 is shorted to GND when FC cart inserted
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// and jumper closed..
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// Believe I closed this jumper on units I shipped
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// prob should have left it open..
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// Suggested fix: leave open and ground EXP9
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// -prevents issue with LED when FC cart inserted
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// -minor draw back no access to EXP9
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// ALOG - EXP6 - DIGI jumper
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// another noob jumper decision...
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// ALOG is the MCU AREF pin which should be tied to VCC
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// -I thought it was an analog in apparently...
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// DIGI is EXP flip flop Q6 output
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// Best position for this jumper is EXP6-DIGI
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// ALOG pad should be tied to VCC with jumper..
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// Doing that would make it similar to future designs.
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// Don't think I shipped any with ALOG jumper closed
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// NES EXP6 is tied to Famicom pin 46 (Sound to RF)
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// Expansion port FlipFlop /OE - CLK
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// Aside from lame jumper design above, biggest difference
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// between this PCB version and future ones.
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// -EXP FF /OE controlled by MCU PD7
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// -EXP FF CLK controlled by MCU PC3
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// Future versions control both /OE and CLK with PD7
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// -this frees PC3 for user use
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// Both FlipFlops D i/p are driven by Data bus (PORT B)
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//
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//
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// Second printed circuit board version
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// only handful made (about a dozen?)
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// Purple solder mask
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// Labeled "Kazzo PCB rev 1.1"
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// Dated 8/22/2011
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// * Only contained NES and Famicom connectors
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// * Identical to version above aside from the following
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// * Corrected bug where USB data lines mixed up
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// * Changed silkscreen to v1.1 as suggested by naruko
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// * INPUT/OUTPUT differences:
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// -Same as version above as far as I know.
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//
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//
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// uncomment define if buiding for this versions
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//#define GREEN_KAZZO
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//
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// Third printed circuit board version
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// only handful made (about ten?) used primarily as SNES prototype
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// Green solder mask
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// Labeled "Retro programmer/dumper v1.2" "Kazzo 1.x"
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// Dated Apr 2013
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// * First version to add SNES connector along with NES & FC
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// * Removed noob jumpers from purple versions above.
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// -grouned FC pin16 as it should have been.
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// * INPUT/OUTPUT differences:
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// -EXP FF /OE still controlled by MCU PD7
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// -MCU PC7 controls both CLK on both FF's.
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// -EXP FF D inputs are PORTA
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// all other versions are driven by PORTB
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// This means you always have to clock both flipflops
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// Place desired value on PORTA/B respectively and clock with PD7
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// -PC3 is free for user use.
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// -SNES /RESET pin not controlled by PD0 (EXP0)
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// instead it's controlled by A20 (EXPFF Q4)
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// prevents putting INL SNES boards in program mode unless A20 is also low
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// pretty much makes flashing SNES boards a royal PITA/impossible
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// Suggested fix is to have PD0 (EXP0) control SNES /RESET
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// would have to free /RESET and wire to EXP0/PD0 to permit flashing/reading INL SNES board.
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//
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//
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// Fourth printed circuit board version
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// First volume PCB run ~300 copies
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// Yellow solder mask
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// Labeled "Retro programmer/dumper v1.2b" "Kazzo 1.x"
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// Dated May 2013
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// * Includes NES, Famicom, & SNES connector
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// * SNES board must be removed from case and slid all the way to right
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// * Pitch offset on SNES connector makes it difficult to connect with original SNES boards.
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// -Connector designed to only provide support for INL SNES Hi/Lo-ROM boards.
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// * Care must be excersized not to insert SNES board backwards applying reverse power.
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// * Effectively Final circuit design after lessons learned on small batches that preceeded.
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// * INPUT/OUTPUT differences:
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// -EXP FF /OE & CLK controlled by MCU PD7
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// -MCU PC7 only controls CLK on ADDR HIGH FF.
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// -EXP & ADDRHI FF D inputs both on Data bus PORTB
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// -PC3 is free for user use.
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// -SNES /RESET pin controlled by PD0 (EXP0)
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// -Retains prev ver fixes, nothing funny going on with jumpers FC GND pin #16
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//
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//
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// Fifth printed circuit board version
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// Second volume PCB run ~500 copies
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// Yellow solder mask
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// Labeled "Retro programmer/dumper v1.2b" "Kazzo 1.x"
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// Dated OCT 2014
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// * Includes NES, Famicom, & SNES connector
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// * SNES connector setup/cautions just like the prev version.
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// * No significant changes from previous version.
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// -Changed MCU clock to Crystal instead of resonator in prev ver.
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// -Added screw mount holes, although not very well placed.
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// * INPUT/OUTPUT differences:
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// -None from previous version
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//
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//
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// Sixth printed circuit board version
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// Third volume PCB run in production as of 1NOV2016
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// Orange solder mask
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// Labeled "Retro programmer/dumper v1.4" "Kazzo 1.x"
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// Dated OCT 2016
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// Addition of fancy INL logo for first time
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// * Includes NES, Famicom, & SNES connector
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// * SNES connector improvement to correct pitch issue with prev ver.
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// * Addition of PCT resettable fuse on incoming power.
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// -Provides protection to SNES boards inserted backwards.
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// * Rearrangement of BL/RUN switch and screw holes for better case design.
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// * Cut out buzzer pads (PD6) from under MCU which was never developed.
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// * INPUT/OUTPUT differences:
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// -None from previous version
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//
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//
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// STM32F070C6T6 KAZZO USB 2.0 ADAPTER board
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// designed to retrofit all previous kazzo versions
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// updates to arm cortex M0 core and hardware USB 2.0
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// Green solder mask
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// Labeled "KAZZO USB 2.0 ADAPTER" "V1.P"
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// Dated JAN 2017
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// Pins out to all DIP-40 pins:
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// AVR reset -> STM reset
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// AVR BOOTLOADn -> STM BOOT0 (not sure if this actually works...)
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// AVR XTAL1/2 -> STM oscOUT/IN (PF1/0)
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//
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// ascii art board connections setup:
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//AVR PIN #40<. .-> AVR PIN #20
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// __|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|__|_
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// | O O O O O O O O O O O O O O O O O O O O|
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// | "KAZZO USB 2.0 ADAPTER" |
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// kazzo | programming header /\ 6pin extra port | kazzo
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// rst butn | O- /RESET / \ EMPTY -O O- PA6 | AVR PA6 "FREE"
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// CIRAM_A10| O- SWD (PA13) CIRAM A10 /STM \ EMPTY -O O- PC15 | nc
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// GND | O- GND \ 32 / 3v3 -O O- PC14 | nc
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// nc | O- SWC (PA14) \ ./ GND -O O- PA1 | nc
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// nc | O- 3v3 \/ 5v -O O- PA0 | EXP0
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// | |
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// | O O O O O O O O O O O O O O O O O O O O|
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// -------------------------------------------------------------
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// | | | | | | | | | | | | | | | | | | | |
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//AVR PIN #1<-` `-> AVR PIN #19
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// STM32 GPIO registers are quite different than AVR style
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// they are more flexible/capable, but a little tricky to interface with
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// some features present on STM32 pins, but not AVR
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// - PULL-DOWN ability (and PULL-UP like AVR)
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// - Speed/Slew rate selection
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// - Open drain outputs (and push/pull like AVR)
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// - Bit set/reset registers to remove necessity of RMW operations
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// - Lockability to keep port config bits from changing until reset
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// - GPIO blocks must be provided a clock and enabled to "turn on"
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// failing to do so will cause hard faults when accessing registers!!
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//
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// All GPIO registers can be accessed in byte, halfword, or 32bit full words
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// unless otherwise noted
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//
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// GPIOx->MODER[1:0] 32bit registers control direction/type of driver
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// 00- Input (default reset state, except SWC-PA15 & SWD-PA13 default AF)
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// 01- Gen Purp Output
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// 10- Alternate func (SPI, I2C, etc)
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// 11- reserved
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// MODER[1] typically leave clear unless using AltFunc
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// MODER[0] becomes equivalent of AVR DDR
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//
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// GPIOx->OTYPER 16bit registers control driver type
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// 0- Push Pull (default reset state)
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// 1- Open Drain
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use pushpull as AVR does
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//
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// GPIOx->OSPEEDR[1:0] 32bit registers control pin driver speed/slew
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// x0- Low speed (default reset state, except SWD-PA13 default High Spd)
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// 01- Medium speed
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// 11- High speed
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// N/A when MODER is set to "00" INPUT
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// we can generally just ignore this register and use slow speed
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//
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// GPIOx->PUPDR[1:0] 32bit registers control pull-up/down resistors
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// this register is in effect even when alternate functions are enabled
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// 00- floating/disabled, no pull-up/down (default for most pins except below)
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// 01- Pull-up enabled (default SWD-PA13) also CIRAM A10
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// 10- Pull-down enabled (default SWC-PA14)
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// 11- Reserved, don't use (prob enables both which would be bad...)
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// PUPDR[0] is kinda like AVR PORT when DDR is set to INPUT, and PUPDR[1]=0
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// This ends up being a little cleaner than AVR i/o interfacing
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// Can probably just enable pull-ups on everything and leave it like that
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// -only exception being USB pins (PA11/12) better leave those floating
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//
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// GPIOx->IDR 16bit register used to read current input level on pin
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// this register is read only
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//
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// GPIOx->ODR 16bit register used to set output of pin if enabled by MODER
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// this register is read/writeable
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//
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// GPIOx->BSSR 32bit register to only set/clear pins
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// BR[31:16] upper halfword is will reset/clear pin if written to '1' value
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// BS[15:00] lower halfword is will set pin if written to '1' value
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// writing 0 to any bit has no effect
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// if setting both BS register has priority (bit will be set)
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// this register is write only!
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//
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// GPIO->BRR 16bit register equivalent to upper word of BSSR register above
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// provides convinent separate BR register that doesn't need shifted
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//
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// GPIOx->LCKR 17bit register MUST BE ACCESSED in 32bit full words!!!
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// complex sequence needed to set, but once done lock config/altfunc
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// bits for that GPIO. I interpret this to mean the registers above
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// with exception of IDR, ODR, BSSR registers, plus AF registers
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// Good to use this for things than we don't want to accidentally change:
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// - USB & XTAL pins come to mind as good candidates
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//
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// GPIOx->AFRL/H 2 sets of 32bit registers to determine alternate function
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// of GPIO if enabled with MODER registers. Default is AF0 at reset
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//
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// Following macros are written to be supported on all yellow/orange silk kazzos
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// includes rev 1.2b & 1.4 Dated May 2013 and later
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// used for a very short delay
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#define NOP() do { __asm__ __volatile__ ("nop"); } while (0)
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////PORT wide set/clear
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//#define LO 0x00
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//#define HI 0xFF
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//
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////DDR values
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//#define IP 0x00
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//#define OP 0xFF
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//
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////============================
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////ADDR[7:0] PORTA
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////============================
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////PORT DEFN
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//#define ADDR_OUT PORTA
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//#define ADDR_IN PINA
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//#define ADDR_DDR DDRA
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////DDR-PORT MACROS
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//#define _ADDR_IP() ADDR_DDR = IP
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//#define _ADDR_OP() ADDR_DDR = OP
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//#define _ADDR_LO() ADDR_OUT = LO
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//#define _ADDR_HI() ADDR_OUT = HI
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//
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//Need to rethink these macros.. Curently AVR uses them as values
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//But for the stm32 it makes more sense to create function macros
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//function macros could be made compatible with AVR as well
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//ADDR_OUT = addrL; data[i] = DATA_IN;
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//would become:
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//ADDR_OUT(addrL); DATA_IN(data[i]);
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//
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//The port wide HI/LO IP/OP macros don't work either as we can't define values
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//
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//Firmware macro "functions" have underscore prefix
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//opcode macros have identical name but without the prefix
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//Haven't decided if PIN/PORT macros should be given underscore as well.
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// Good chance I will want them with _ when writing read functions
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// Easier to add them than take them out maybe..?
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//Current rule is _ goes with () type macro
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//Thinking this may as well change too since doing away with value macros...
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//Or perhaps leading underscore denotes macros w/o operands
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//PORT wide set/clear
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#define AVR_LO 0x00
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#define AVR_HI 0xFF
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//DDR values
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#define AVR_IP 0x00
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#define AVR_OP 0xFF
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//============================
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//ADDR[7:0] PORTA
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//============================
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//PORT DEFN
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#define ADDR_OUT(op) (PORTA = op)
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#define ADDR_IN(op) (op = PINA)
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#define ADDR_DDR(op) (DDRA = op)
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//AND/OR functions
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#define ADDR_OUT_OR(op) (PORTA |= op)
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#define ADDR_OUT_AND(op) (PORTA &= op)
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//DDR-PORT MACROS
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#define ADDR_IP() ADDR_DDR = AVR_IP
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#define ADDR_OP() ADDR_DDR = AVR_OP
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#define ADDR_LO() ADDR_OUT = AVR_LO
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#define ADDR_HI() ADDR_OUT = AVR_HI
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//============================
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//DATA[7:0] PORTB
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//============================
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//PORT DEFN
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#define DATA_OUT PORTB
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#define DATA_IN PINB
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#define DATA_DDR DDRB
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//DDR-PORT MACROS
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#define _DATA_IP() DATA_DDR = IP
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#define _DATA_OP() DATA_DDR = OP
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#define _DATA_LO() DATA_OUT = LO
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#define _DATA_HI() DATA_OUT = HI
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//============================
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//CTL PORTC
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//============================
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//PORT DEFN
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#define CTL_OUT PORTC
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#define CTL_IN PINC
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#define CTL_DDR DDRC
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//DDR-PORT MACROS
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#define _CTL_IP() CTL_DDR = IP
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// No CTL_OP() macro as some of these are inputs or bidir, best to individually assert as output
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#define _CTL_LO() CTL_OUT = LO
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#define _CTL_HI() CTL_OUT = HI
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//PIN DEFN
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#define M2 PC0 //NES, FC, & SNES (SYSCLK)
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#define ROMSEL PC1 //(aka PRG/CE) NES, FC, & SNES
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#define PRGRW PC2 //PRG R/W on NES & FC
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#ifdef PURPLE_KAZZO
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#define p_AXL PC3 //EXP FF CLK on purple boards
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#else
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#define FREE PC3 //Free pin on all other boards
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#endif
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#define CSRD PC4 //NES & FC CHR /RD, SNES /RD
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#define CSWR PC5 //NES & FC CHR /WR, SNES /WR
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#define CICE PC6 //NES & FC CIRAM /CE, most carts are 2screen tying this to CHR /A13 making this an I/P
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#ifdef GREEN_KAZZO
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#define g_AXHL PC7 //Both ADDR_MID & EXP/ADDRHI FF CLK on green prototype
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#else
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#define AHL PC7 //ADDR MID FF CLK per orig kazzo design
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#endif
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//PIN MACROS
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#define _M2_IP() CTL_DDR &= ~(1<<M2)
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#define _M2_OP() CTL_DDR |= (1<<M2)
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#define _M2_LO() CTL_OUT &= ~(1<<M2)
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#define _M2_HI() CTL_OUT |= (1<<M2)
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//TODO read M2 PIN as input
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#define _ROMSEL_IP() CTL_DDR &= ~(1<<ROMSEL)
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#define _ROMSEL_OP() CTL_DDR |= (1<<ROMSEL)
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#define _ROMSEL_LO() CTL_OUT &= ~(1<<ROMSEL)
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#define _ROMSEL_HI() CTL_OUT |= (1<<ROMSEL)
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#define _PRGRW_IP() CTL_DDR &= ~(1<<PRGRW)
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#define _PRGRW_OP() CTL_DDR |= (1<<PRGRW)
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#define _PRGRW_WR() CTL_OUT &= ~(1<<PRGRW) //LO for writes
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#define _PRGRW_RD() CTL_OUT |= (1<<PRGRW) //HI for reads
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#ifdef PURPLE_KAZZO
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#define _p_AXL_ip() CTL_DDR &= ~(1<<p_AXL) //Don't use these, use software tied together versions instead.
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#define _p_AXL_op() CTL_DDR |= (1<<p_AXL) //Increases compatibility between versions
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#define _p_AXL_lo() CTL_OUT &= ~(1<<p_AXL) //Don't recommend calling lo/hi, use CLK instead
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#define _p_AXL_hi() CTL_OUT |= (1<<p_AXL)
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//_AXL_CLK assumes AXL was previously left in default low state
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#define _AXL_CLK() _p_AXL_hi(); _p_AXL_lo(); //same name and convention on final design
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#else //Green and final design
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#define _FREE_IP() CTL_DDR &= ~(1<<FREE)
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#define _FREE_OP() CTL_DDR |= (1<<FREE)
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#define _FREE_LO() CTL_OUT &= ~(1<<FREE)
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#define _FREE_HI() CTL_OUT |= (1<<FREE)
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#endif
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#define _CSRD_IP() CTL_DDR &= ~(1<<CSRD)
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#define _CSRD_OP() CTL_DDR |= (1<<CSRD)
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#define _CSRD_LO() CTL_OUT &= ~(1<<CSRD)
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#define _CSRD_HI() CTL_OUT |= (1<<CSRD)
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#define _CSWR_IP() CTL_DDR &= ~(1<<CSWR)
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#define _CSWR_OP() CTL_DDR |= (1<<CSWR)
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#define _CSWR_LO() CTL_OUT &= ~(1<<CSWR)
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#define _CSWR_HI() CTL_OUT |= (1<<CSWR)
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#define _CICE_IP() CTL_DDR &= ~(1<<CICE)
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#define _CICE_OP() CTL_DDR |= (1<<CICE)
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#define _CICE_LO() CTL_OUT &= ~(1<<CICE)
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#define _CICE_HI() CTL_OUT |= (1<<CICE)
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#ifdef GREEN_KAZZO
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#define _g_AXHL_IP() CTL_DDR &= ~(1<<g_AXHL)
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#define _g_AXHL_OP() CTL_DDR |= (1<<g_AXHL)
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#define _g_AXHL_lo() CTL_OUT &= ~(1<<g_AXHL) //Don't recommend calling these as AXHL should be left low
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#define _g_AXHL_hi() CTL_OUT |= (1<<g_AXHL) //That way _AXHL_CLK(); is always effective
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#define _AXHL_CLK() _g_AXHL_hi(); _g_AXHL_lo();
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#define _AHL_CLK() software_AHL_CLK();
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#define _AXL_CLK() software_AXL_CLK();
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//can ~safely consider this pin as if it were only AHL due to software AHL/AXL CLK
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#define _AHL_IP() _g_AXHL_IP();
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#define _AHL_OP() _g_AXHL_OP();
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#define _AHL_lo() _g_AXHL_lo();
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#define _AHL_hi() _g_AXHL_hi();
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#else //purple and final design
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#define _AHL_IP() CTL_DDR &= ~(1<<AHL)
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#define _AHL_OP() CTL_DDR |= (1<<AHL)
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#define _AHL_lo() CTL_OUT &= ~(1<<AHL) //Don't recommend calling these as AHL should be left low
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#define _AHL_hi() CTL_OUT |= (1<<AHL) //That way _AHL_CLK(); is always effective
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#define _AHL_CLK() _AHL_hi(); _AHL_lo();
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#endif
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//green board software AXL & AHL are separated in software in pinport.c
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//============================
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//AUX PORTD
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//============================
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//PORT DEFN
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#define AUX_OUT PORTD
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#define AUX_IN PIND
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#define AUX_DDR DDRD
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//DDR-PORT MACROS
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#define _AUX_IP() AUX_DDR &= ((1<<USBP) | (1<<USBM)) //Don't touch USB pins!!!
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// No AUX_OP() macro as many of these are inputs or bidir, best to individually assert as output
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#define _AUX_LO() AUX_OUT &= ((1<<USBP) | (1<<USBM))
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#define _AUX_HI() AUX_OUT |= ~((1<<USBP) | (1<<USBM))
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//PIN DEFN
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#define EXP0 PD0 //NES EXP0 controls a number of varying flash cart features...
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#define FC_APU PD0 //FC Audio in cart from 2A03 APU
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#define TDO PD0 //CPLD JTAG on INL-ROM NES/FC boards released after ~Oct2016
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#define SRST PD0 //SNES /RESET pin used for CPLD prgm/play mode and SRAM CE
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#define LED PD1 //LED on INL retro prog-dumper
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#define EXP9 PD1 //NES dual purposed pin
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#define USBP PD2 //USB D+ don't touch this pin!
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#define IRQ PD3 //Connected to NES, FC, & SNES
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#define USBM PD4 //USB D- don't touch this pin!
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#define CIA10 PD5 //NES & FC CIRAM A10 (aka VRAM A10)
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#define BL PD6 //Bootloader switch BL->GND, RUN->float
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#ifdef PURPLE_KAZZO
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#define pg_XOE PD7 //EXP/ADDRHI FF /OE pin on purple and green boards
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#endif
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#ifdef GREEN_KAZZO
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#define pg_XOE PD7 //EXP/ADDRHI FF /OE pin on purple and green boards
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#endif
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#ifndef pg_XOE //FINAL_DESIGN
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#define AXLOE PD7 //EXP/ADDRHI FF CLK & /OE pin on final board versions
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#endif
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//PIN MACROS
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//lower case aren't meant to be called unless certain pin is 5v tolerant
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#define _EXP0_ip() AUX_DDR &= ~(1<<EXP0)
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#define _EXP0_op() AUX_DDR |= (1<<EXP0)
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#define _EXP0_lo() AUX_OUT &= ~(1<<EXP0) //Don't call this assuming EXP0 DDR is set to o/p
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#define _EXP0_hi() AUX_OUT |= (1<<EXP0) //Don't call this unless you're certain pin is 5v tolerant
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//User options pull up, force low, and float
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#define _EXP0_LO() _EXP0_lo(); _EXP0_op(); //Sets low then DDR to o/p
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#define _EXP0_PU() _EXP0_ip(); _EXP0_hi(); //maybe add some NOP() to allow time for pull up
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#define _EXP0_FLT() _EXP0_ip(); _EXP0_lo(); //Set to i/p w/o pullup
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//SNES /RESET versions, more permissible for driving EXP0 to 5v as NES cart shouldn't be inserted
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#define _SRST_IP() _EXP0_ip()
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#define _SRST_OP() _EXP0_op()
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#define _SRST_LO() _EXP0_lo()
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#define _SRST_HI() _EXP0_hi()
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#define _LED_IP() AUX_DDR &= ~(1<<LED)
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#define _LED_OP() AUX_DDR |= (1<<LED)
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#define _LED_OFF() AUX_OUT &= ~(1<<LED)
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#define _LED_ON() AUX_OUT |= (1<<LED)
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#define _IRQ_IP() AUX_DDR &= ~(1<<IRQ)
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#define _IRQ_OP() AUX_DDR |= (1<<IRQ)
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#define _IRQ_LO() AUX_OUT &= ~(1<<IRQ)
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#define _IRQ_HI() AUX_OUT |= (1<<IRQ)
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#define _CIA10_IP() AUX_DDR &= ~(1<<CIA10)
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#define _CIA10_OP() AUX_DDR |= (1<<CIA10)
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#define _CIA10_LO() AUX_OUT &= ~(1<<CIA10)
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#define _CIA10_HI() AUX_OUT |= (1<<CIA10)
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#define _BL_IP() AUX_DDR &= ~(1<<BL)
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#define _BL_OP() AUX_DDR |= (1<<BL)
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#define _BL_LO() AUX_OUT &= ~(1<<BL)
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#define _BL_HI() AUX_OUT |= (1<<BL)
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//purple and green versions
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#if ( (defined(PURPLE_KAZZO)) || (defined(GREEN_KAZZO)) )
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#define _XOE_ip() AUX_DDR &= ~(1<<pg_XOE) //don't use these, use software tied together AXLOE instead
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#define _XOE_op() AUX_DDR |= (1<<pg_XOE)
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#define _XOE_lo() AUX_OUT &= ~(1<<pg_XOE) //FF /OE pin low->enable o/p
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#define _XOE_hi() AUX_OUT |= (1<<pg_XOE) //FF /OE pin high->disable o/p
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#else //FINAL_DESIGN
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#define _AXLOE_IP() AUX_DDR &= ~(1<<AXLOE)
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#define _AXLOE_OP() AUX_DDR |= (1<<AXLOE)
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#define _EXPFF_OP() AUX_OUT &= ~(1<<AXLOE) //FF /OE pin low->enable o/p
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#define _EXPFF_FLT() AUX_OUT |= (1<<AXLOE) //FF /OE pin high->disable o/p
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//Caution _AXL_CLK() relies on _EXPFF_OP() to be called beforehand
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// Think of it like you must enable the output before you can clock it.
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// Floating EXPFF also happens to clock it. Think of it like it looses it's value if disabled.
|
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#define _AXL_CLK() _EXPFF_FLT(); _EXPFF_OP(); //same name and convention as purple
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#endif
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|
|
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//Final version ties XOEn and AXL to same pin, we can do this in software to make other ver behave similarly
|
|
#ifdef PURPLE_KAZZO
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|
#define _AXLOE_IP() _XOE_ip(); _p_AXL_ip();
|
|
#define _AXLOE_OP() _XOE_op(); _p_AXL_op();
|
|
#define _EXPFF_OP() _XOE_lo(); _p_AXL_lo();
|
|
#define _EXPFF_FLT() _XOE_hi(); _p_AXL_hi();
|
|
#endif
|
|
#ifdef GREEN_KAZZO //green can't tie AXL, just don't worry about clocking effect while enabling/disabling
|
|
#define _AXLOE_IP() _XOE_ip(); //run risk that AHL isn't O/P because AXL was made O/P instead
|
|
#define _AXLOE_OP() _XOE_op(); //sofware AXL/AHL clock covers this case though.
|
|
#define _EXPFF_OP() _XOE_lo();
|
|
#define _EXPFF_FLT() _XOE_hi();
|
|
#endif
|
|
|
|
|
|
//clocks must be initialized, Data bus clear
|
|
#define _ADDRH_SET(oper) _DATA_OP(); DATA_OUT = oper; _AHL_CLK(); _DATA_IP();
|
|
#define _ADDRX_SET(oper) _DATA_OP(); DATA_OUT = oper; _AXL_CLK(); _DATA_IP();
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|
|
|
//PPU A13 is ADDRH bit 5
|
|
#define PPU_A13 0x20
|
|
//PPU /A13 is ADDRH bit 7
|
|
#define PPU_A13N 0x80
|
|
|
|
//PPU and CPU
|
|
#define A10 0x04
|
|
#define A11 0x08
|
|
|
|
#endif
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