482 lines
12 KiB
C
482 lines
12 KiB
C
#include "nes.h"
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//=================================================================================================
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//
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// NES operations
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// This file includes all the nes functions possible to be called from the nes dictionary.
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//
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// See description of the commands contained here in shared/shared_dictionaries.h
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//
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//=================================================================================================
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/* Desc:Function takes an opcode which was transmitted via USB
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* then decodes it to call designated function.
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* shared_dict_nes.h is used in both host and fw to ensure opcodes/names align
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* Pre: Macros must be defined in firmware pinport.h
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* opcode must be defined in shared_dict_nes.h
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* Post:function call complete.
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* Rtn: SUCCESS if opcode found and completed, error if opcode not present or other problem.
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*/
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uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata )
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{
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#define RD_LEN 0
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#define RD0 1
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#define RD1 2
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#define BYTE_LEN 1
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#define HWORD_LEN 2
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switch (opcode) {
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// //no return value:
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case DISCRETE_EXP0_PRGROM_WR:
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discrete_exp0_prgrom_wr( operand, miscdata );
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break;
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case NES_PPU_WR:
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nes_ppu_wr( operand, miscdata );
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break;
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case NES_CPU_WR:
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nes_cpu_wr( operand, miscdata );
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break;
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//8bit return values:
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// case EMULATE_NES_CPU_RD:
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// *data = emulate_nes_cpu_rd( addrH, addrL );
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// break;
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case NES_CPU_RD:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = nes_cpu_rd( operand );
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break;
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case NES_PPU_RD:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = nes_ppu_rd( operand );
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break;
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case CIRAM_A10_MIRROR:
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rdata[RD_LEN] = BYTE_LEN;
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rdata[RD0] = ciram_a10_mirroring( );
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break;
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default:
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//macro doesn't exist
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return ERR_UNKN_NES_OPCODE;
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}
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return SUCCESS;
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}
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/* Desc: Discrete board PRG-ROM only write, does not write to mapper
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* PRG-ROM /WE <- EXP0 w/PU
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* PRG-ROM /OE <- /ROMSEL
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* PRG-ROM /CE <- GND
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* PRG-ROM write: /WE & /CE low, /OE high
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* mapper '161 CLK <- /ROMSEL
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* mapper '161 /LOAD <- PRG R/W
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* mapper '161 /LOAD must be low on rising edge of CLK to latch data
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* This is a /WE controlled write. Address latched on falling edge,
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* and data latched on rising edge EXP0
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* Note:addrH bit7 has no effect (ends up on PPU /A13)
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* /ROMSEL, M2, & PRG R/W signals untouched
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* Pre: nes_init() setup of io pins
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* Post:data latched by PRG-ROM, mapper register unaffected
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* address left on bus
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* data left on bus, but pullup only
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* EXP0 left pulled up
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* Rtn: None
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*/
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void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
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{
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ADDR_SET(addr);
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DATA_OP();
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DATA_SET(data);
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EXP0_OP(); //Tas = 0ns, Tah = 30ns
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EXP0_LO();
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EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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//16Mhz avr clk = 62.5ns period guarantees timing reqts
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DATA_IP();
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}
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//
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// /* Desc:Emulate NES CPU Read as best possible
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// * decode A15 from addrH to set /ROMSEL as expected
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// * float EXP0
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// * toggle M2 as NES would
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// * insert some NOP's in to be slow like NES
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// * Note:not the fastest read operation
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// * Pre: nes_init() setup of io pins
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// * Post:address left on bus
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// * data bus left clear
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// * EXP0 left floating
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// * Rtn: Byte read from PRG-ROM at addrHL
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// */
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// uint8_t emulate_nes_cpu_rd( uint8_t addrH, uint8_t addrL )
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// {
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// uint8_t read; //return value
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//
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// //m2 should be low as it aids in disabling WRAM
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// //this is also m2 state at beginging of CPU cycle
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// //all these pins should already be in this state, but
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// //go ahead and setup just to be sure since we're trying
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// //to be as accurate as possible
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// _EXP0_FLT(); //this could have been left pulled up
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// _M2_LO(); //start of CPU cycle
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// _ROMSEL_HI(); //trails M2
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// _PRGRW_RD(); //happens just after M2
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//
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// //set address bus
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// ADDR_OUT = addrL;
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// _ADDRH_SET(addrH);
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//
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// //couple NOP's to wait a bit
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// NOP();
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// NOP();
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//
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// //set M2 and /ROMSEL
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// if( addrH >= 0x80 ) { //addressing cart rom space
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// _M2_HI();
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// _ROMSEL_LO(); //romsel trails M2 during CPU operations
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// } else {
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// _M2_HI();
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// }
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//
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// //couple more NOP's waiting for data
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// NOP();
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// NOP();
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// NOP();
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// NOP();
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// NOP();
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// NOP();
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//
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// //latch data
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// read = DATA_IN;
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//
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// //return bus to default
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// _M2_LO();
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// _ROMSEL_HI();
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//
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// return read;
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// }
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//
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/* Desc:NES CPU Read without being so slow
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* decode A15 from addrH to set /ROMSEL as expected
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* float EXP0
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* toggle M2 as NES would
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* data bus left clear
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* EXP0 left floating
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* Rtn: Byte read from PRG-ROM at addrHL
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*/
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uint8_t nes_cpu_rd( uint16_t addr )
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{
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uint8_t read; //return value
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//set address bus
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ADDR_SET(addr);
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//set M2 and /ROMSEL
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MCO_HI();
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if( addr >= 0x8000 ) { //addressing cart rom space
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ROMSEL_LO(); //romsel trails M2 during CPU operations
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}
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//couple more NOP's waiting for data
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//zero nop's returned previous databus value
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NOP(); //one nop got most of the bits right
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NOP(); //two nop got all the bits right
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NOP(); //add third nop for some extra
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NOP(); //one more can't hurt
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//might need to wait longer for some carts...
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//latch data
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DATA_RD(read);
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//return bus to default
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MCO_LO();
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ROMSEL_HI();
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return read;
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}
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/* Desc:NES CPU Write
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* Just as you would expect NES's CPU to perform
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* A15 decoded to enable /ROMSEL
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* This ends up as a M2 and/or /ROMSEL controlled write
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* Note:addrH bit7 has no effect (ends up on PPU /A13)
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* EXP0 floating
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* Pre: nes_init() setup of io pins
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* Post:data latched by anything listening on the bus
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* address left on bus
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* data left on bus, but pullup only
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* Rtn: None
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*/
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void nes_cpu_wr( uint16_t addr, uint8_t data )
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{
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//Float EXP0 as it should be in NES
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EXP0_IP_FL();
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//need for whole function
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//_DATA_OP();
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//set addrL
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//ADDR_OUT = addrL;
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//latch addrH
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//DATA_OUT = addrH;
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//_AHL_CLK();
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ADDR_SET(addr);
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//PRG R/W LO
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PRGRW_LO();
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//put data on bus
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DATA_OP();
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DATA_SET(data);
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//set M2 and /ROMSEL
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MCO_HI();
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if( addr >= 0x8000 ) { //addressing cart rom space
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ROMSEL_LO(); //romsel trails M2 during CPU operations
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}
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//give some time
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NOP();
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NOP();
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//latch data to cart memory/mapper
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MCO_LO();
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ROMSEL_HI();
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//retore PRG R/W to default
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PRGRW_HI();
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//Free data bus
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DATA_IP();
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}
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/* Desc:NES PPU Read
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* decode A13 from addrH to set /A13 as expected
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* data bus left clear
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* Rtn: Byte read from CHR-ROM/RAM at addrHL
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*/
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uint8_t nes_ppu_rd( uint16_t addr )
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{
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uint8_t read; //return value
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//addr with PPU /A13
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if (addr < 0x2000) { //below $2000 A13 clear, /A13 set
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addr |= PPU_A13N_WORD;
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} //above PPU $1FFF, A13 set, /A13 clear
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ADDR_SET( addr );
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//set CHR /RD and /WR
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CSRD_LO();
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//couple more NOP's waiting for data
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//zero nop's returned previous databus value
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NOP(); //one nop got most of the bits right
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NOP(); //two nop got all the bits right
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NOP(); //add third nop for some extra
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NOP(); //one more can't hurt
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//might need to wait longer for some carts...
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//latch data
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DATA_RD(read);
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//return bus to default
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CSRD_HI();
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return read;
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}
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/* Desc:NES PPU Write
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* decode A13 from addrH to set /A13 as expected
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* flash: address clocked falling edge, data rising edge of /WE
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* Pre: nes_init() setup of io pins
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* Post:data written to addrHL
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* address left on bus
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* data bus left clear
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* Rtn: None
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*/
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void nes_ppu_wr( uint16_t addr, uint8_t data )
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{
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//addr with PPU /A13
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if (addr < 0x2000) { //below $2000 A13 clear, /A13 set
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addr |= PPU_A13N_WORD;
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} //above PPU $1FFF, A13 set, /A13 clear
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ADDR_SET( addr );
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//put data on bus
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DATA_OP();
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DATA_SET(data);
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NOP();
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//set CHR /RD and /WR
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CSWR_LO();
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//might need to wait longer for some carts...
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NOP(); //one can't hurt
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//latch data to memory
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CSWR_HI();
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//clear data bus
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DATA_IP();
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}
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/* Desc:PPU CIRAM A10 NT arrangement sense
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* Toggle A11 and A10 and read back CIRAM A10
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* report back if vert/horiz/1scnA/1scnB
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* reports nesdev defined mirroring
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* does not report Nintendo's "Name Table Arrangement"
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* Pre: nes_init() setup of io pins
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* Post:address left on bus
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* Rtn: MIR_VERT, MIR_HORIZ, MIR_1SCNA, MIR_1SCNB
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* errors not really possible since all combinations
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* of CIRAM A10 level designate something valid
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*/
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uint8_t ciram_a10_mirroring( void )
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{
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uint16_t readV, readH;
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//set A10, clear A11
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ADDRH(A10_BYTE);
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CIA10_RD(readV);
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//set A11, clear A10
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ADDRH(A11_BYTE);
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CIA10_RD(readH);
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//if CIRAM A10 was always low -> 1 screen A
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if ((readV==0) & (readH==0)) return MIR_1SCNA;
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//if CIRAM A10 was always hight -> 1screen B
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if ((readV!=0) & (readH!=0)) return MIR_1SCNB;
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//if CIRAM A10 toggled with A10 -> Vertical mirroring, horizontal arrangement
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if ((readV!=0) & (readH==0)) return MIR_VERT;
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//if CIRAM A10 toggled with A11 -> Horizontal mirroring, vertical arrangement
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if ((readV==0) & (readH!=0)) return MIR_HORZ;
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//shouldn't be here...
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return GEN_FAIL;
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}
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/* Desc:NES CPU Page Read with optional USB polling
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* decode A15 from addrH to set /ROMSEL as expected
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* float EXP0
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* toggle M2 as NES would
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* if poll is true calls usbdrv.h usbPoll fuction
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* this is needed to keep from timing out when double buffering usb data
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* Pre: nes_init() setup of io pins
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* num_bytes can't exceed 256B page boundary
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* Post:address left on bus
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* data bus left clear
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* EXP0 left floating
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* data buffer filled starting at first to last
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* Rtn: Index of last byte read
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*/
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uint8_t nes_cpu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
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{
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uint8_t i;
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//set address bus
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ADDRH(addrH);
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//set M2 and /ROMSEL
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MCO_HI();
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if( addrH >= 0x80 ) { //addressing cart rom space
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ROMSEL_LO(); //romsel trails M2 during CPU operations
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}
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//set lower address bits
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ADDRL(first); //doing this prior to entry and right after latching
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//extra NOP was needed on stm6 as address hadn't settled in time for the very first read
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NOP();
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//gives longest delay between address out and latching data
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for( i=0; i<=len; i++ ) {
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//testing shows that having this if statement doesn't affect overall dumping speed
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if ( poll == FALSE ) {
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NOP(); //couple more NOP's waiting for data
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NOP(); //one prob good enough considering the if/else
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} else {
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usbPoll(); //Call usbdrv.h usb polling while waiting for data
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}
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//latch data
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DATA_RD(data[i]);
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//set lower address bits
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//ADDRL(++first); THIS broke things, on stm adapter because macro expands it twice!
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first++;
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ADDRL(first);
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}
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//return bus to default
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MCO_LO();
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ROMSEL_HI();
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//return index of last byte read
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return i;
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}
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/* Desc:NES PPU Page Read with optional USB polling
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* decode A13 from addrH to set /A13 as expected
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* if poll is true calls usbdrv.h usbPoll fuction
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* this is needed to keep from timing out when double buffering usb data
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* Pre: nes_init() setup of io pins
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* num_bytes can't exceed 256B page boundary
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* Post:address left on bus
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* data bus left clear
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* data buffer filled starting at first for len number of bytes
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* Rtn: Index of last byte read
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*/
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uint8_t nes_ppu_page_rd_poll( uint8_t *data, uint8_t addrH, uint8_t first, uint8_t len, uint8_t poll )
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{
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uint8_t i;
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if (addrH < 0x20) { //below $2000 A13 clear, /A13 set
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//ADDRH(addrH | PPU_A13N_BYTE);
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//Don't do weird stuff like above! logic inside macro expansions can have weird effects!!
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addrH |= PPU_A13N_BYTE;
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ADDRH(addrH);
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} else { //above PPU $1FFF, A13 set, /A13 clear
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ADDRH(addrH);
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}
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//set CHR /RD and /WR
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CSRD_LO();
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//set lower address bits
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ADDRL(first); //doing this prior to entry and right after latching
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NOP(); //adding extra NOP as it was needed on PRG
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//gives longest delay between address out and latching data
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for( i=0; i<=len; i++ ) {
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//couple more NOP's waiting for data
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if ( poll == FALSE ) {
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NOP(); //one prob good enough considering the if/else
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NOP();
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} else {
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usbPoll();
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}
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//latch data
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DATA_RD(data[i]);
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//set lower address bits
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first ++;
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ADDRL(first);
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}
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//return bus to default
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CSRD_HI();
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//return index of last byte read
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return i;
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}
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