Added quick support to flash HH85 on BNROM.
Dumped/flashed MMX on SNES v3 boards. created discrete_exp0_mapper_wr to try and write to mapper but not flash for discrete boards but doesn't seem to work for some reason so commented out for now.
This commit is contained in:
Paul Black ASUS win7
parent
f7201f44b7
commit
3e2bcea7e8
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@ -27,18 +27,24 @@ uint8_t dump_buff( buffer *buff ) {
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bank = (buff->page_num)>>6;
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//Nomolos bank table @ CC84
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nes_cpu_wr( (0xCC84+bank), bank );
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//nes_cpu_wr( (0xE473+bank), bank );
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buff->cur_byte = nes_cpu_page_rd_poll( buff->data, addrH, buff->id,
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//id contains MSb of page when <256B buffer
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buff->last_idx, ~FALSE );
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break;
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}
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if (buff->mapper == BxROM) {
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if ((buff->mapper == BxROM) || (buff->mapper == CDREAM)) {
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//write bank value to bank table
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//page_num shift by 7 bits A15 >> A8(0)
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bank = (buff->page_num)>>7;
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//Lizard bank table @ FF94
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nes_cpu_wr( (0xFF94+bank), bank );
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//nes_cpu_wr( (0xFF94+bank), bank );
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//HH85
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nes_cpu_wr( (0xFFE0+bank), bank );
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//Mojon bank table @ FF94
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//nes_cpu_wr( 0x800C, 0x00); //select first bank (only one with table)
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//nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank
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}
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if (buff->mapper == A53) {
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//write bank value to bank table
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@ -49,18 +49,18 @@ uint8_t write_page( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t unlo
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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// if (read == buff->data[n]) {
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n++;
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cur++;
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// LED_IP_PU();
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// LED_LO();
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// } else {
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// nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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// nes_cpu_wr(0x8000, bank); //outer bank
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// nes_cpu_wr(0x5000, 0x00); //chr reg select act like CNROM
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// LED_OP();
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// LED_HI();
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// }
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// if (read == buff->data[n]) {
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n++;
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cur++;
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// LED_IP_PU();
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// LED_LO();
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// } else {
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// nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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// nes_cpu_wr(0x8000, bank); //outer bank
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// nes_cpu_wr(0x5000, 0x00); //chr reg select act like CNROM
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// LED_OP();
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// LED_HI();
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// }
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}
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@ -81,6 +81,7 @@ uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t
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//select first bank for unlock sequence
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//needs to be written to bank table!
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nes_cpu_wr( (0xCC84), 0x00 );
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// nes_cpu_wr( (0xE473), 0x00 );
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//wr_func( 0x5555, 0xAA );
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wr_func( unlock1, 0xAA );
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@ -92,6 +93,7 @@ uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t
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//now need to select bank for the actual write!
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//but this write can't be applied to the PRG-ROM
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nes_cpu_wr( (0xCC84+bank), bank );
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// nes_cpu_wr( (0xE473+bank), bank );
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wr_func( ((addrH<<8)| n), buff->data[n] );
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@ -103,18 +105,15 @@ uint8_t write_page_bank( uint8_t bank, uint8_t addrH, uint16_t unlock1, uint16_t
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//retry if write failed
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//this helped but still seeing similar fails to dumps
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// if (read == buff->data[n]) {
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n++;
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cur++;
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// LED_IP_PU();
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// LED_LO();
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// } else {
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// nes_cpu_wr(0x5000, 0x81); //outer reg select mode
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// nes_cpu_wr(0x8000, bank); //outer bank
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// nes_cpu_wr(0x5000, 0x00); //chr reg select act like CNROM
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// LED_OP();
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// LED_HI();
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// }
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if (read == buff->data[n]) {
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n++;
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cur++;
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LED_IP_PU();
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LED_LO();
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} else {
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LED_OP();
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LED_HI();
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}
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}
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@ -525,16 +524,20 @@ uint8_t flash_buff( buffer *buff ) {
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//write bank value
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//page_num shift by 6 bits A14 >> A8(0)
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bank = buff->page_num >> 6;
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//Nomolos banktable location
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nes_cpu_wr( (0xCC84+bank), bank );
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//bank gets written inside flash algo
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write_page_bank( bank, addrH, 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
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}
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if (buff->mapper == BxROM) {
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if ((buff->mapper == BxROM) || (buff->mapper == CDREAM)) {
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//write bank value
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//page_num shift by 7 bits A15 >> A8(0)
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bank = buff->page_num >> 7;
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//Lizard banktable location
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nes_cpu_wr( (0xFF94+bank), bank );
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//nes_cpu_wr( (0xFF94+bank), bank );
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//hh85
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nes_cpu_wr( (0xFFE0+bank), bank );
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//Mojontales
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//nes_cpu_wr( 0x800C, 0x00); //select first bank (only bank with table)
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//nes_cpu_wr( (0xCC43+bank), bank ); //then select desired bank
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write_page( 0, (0x80 | addrH), 0x5555, 0x2AAA, buff, discrete_exp0_prgrom_wr, nes_cpu_rd );
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}
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if (buff->mapper == A53) {
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@ -38,6 +38,9 @@ uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *r
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case NES_CPU_WR:
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nes_cpu_wr( operand, miscdata );
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break;
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// case DISCRETE_EXP0_MAPPER_WR:
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// discrete_exp0_mapper_wr( operand, miscdata );
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// break;
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//8bit return values:
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// case EMULATE_NES_CPU_RD:
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@ -98,6 +101,114 @@ void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data )
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DATA_IP();
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}
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/* Desc: Discrete board MAPPER write without bus conflicts
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* will also write to PRG-ROM, but PRG-ROM shouldn't output
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* data while writting to mapper. Thus removing need for bank table.
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* NOTE: I think it would be possible to write one value to mapper
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* and another value to PRG-ROM.
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* PRG-ROM /WE <- EXP0 w/PU
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* PRG-ROM /OE <- /ROMSEL
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* PRG-ROM /CE <- GND
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* PRG-ROM write: /WE & /CE low, /OE high
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* mapper '161 CLK <- /ROMSEL
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* mapper '161 /LOAD <- PRG R/W
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* mapper '161 /LOAD must be low on rising edge of CLK to latch data
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* Note:addrH bit7 has no effect (ends up on PPU /A13)
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* M2 signal untouched
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* Pre: nes_init() setup of io pins
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* Post:data latched by MAPPER, will also be written to PRG-ROM afterwards
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* address left on bus
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* data left on bus, but pullup only
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* EXP0 left pulled up
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* Rtn: None
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*/
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//void discrete_exp0_mapper_wr( uint16_t addr, uint8_t data )
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//{
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// //Float EXP0 as it should be in NES
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// EXP0_IP_FL();
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// //EXP0_OP(); //tas = 0ns, tah = 30ns
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// //EXP0_LO();
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//
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// //need for whole function
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// //_DATA_OP();
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//
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// //set addrL
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// //ADDR_OUT = addrL;
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// //latch addrH
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// //DATA_OUT = addrH;
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// //_AHL_CLK();
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// ADDR_SET(addr);
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//
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// //PRG R/W LO
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// PRGRW_LO();
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//
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// //put data on bus
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// DATA_OP();
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// DATA_SET(data);
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//
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// //set M2 and /ROMSEL
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// MCO_HI();
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// if( addr >= 0x8000 ) { //addressing cart rom space
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// ROMSEL_LO(); //romsel trails M2 during CPU operations
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// }
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//
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// //give some time
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// NOP();
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// NOP();
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//
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// //latch data to cart memory/mapper
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// MCO_LO();
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// ROMSEL_HI();
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//
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// //retore PRG R/W to default
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// PRGRW_HI();
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//
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// EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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// //Free data bus
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// DATA_IP();
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//
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// return;
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//
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// /*
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// ADDR_SET(addr);
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//
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// DATA_OP();
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// DATA_SET(data);
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//
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// //start write to PRG-ROM (latch address)
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// exp0_op(); //tas = 0ns, tah = 30ns
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// exp0_lo();
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//
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// //enable write to mapper PRG R/W LO
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// PRGRW_LO();
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// ROMSEL_LO(); //fact that it's low for such a short time might also if PRG-ROM does output data
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//
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// //clock mapper register, should not enable PRG-ROM output since /WE low
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// NOP(); //AVR didn't need this delay
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// NOP(); //AVR didn't need this delay
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// ROMSEL_HI(); //data latched on rising edge
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//
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// //Could output other data here that would like to be written to PRG-ROM
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// //I'm not certain an actual write gets applied to PRG-ROM as /OE is supposed to be high whole time..
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//
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// NOP(); //AVR didn't need this delay
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// //return to default
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// PRGRW_HI();
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//
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// EXP0_IP_PU(); //Twp = 40ns, Tds = 40ns, Tdh = 0ns
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// //16Mhz avr clk = 62.5ns period guarantees timing reqts
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// DATA_IP();
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// */
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//}
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//
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// /* Desc:Emulate NES CPU Read as best possible
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// * decode A15 from addrH to set /ROMSEL as expected
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@ -9,6 +9,7 @@
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uint8_t nes_call( uint8_t opcode, uint8_t miscdata, uint16_t operand, uint8_t *rdata );
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void discrete_exp0_prgrom_wr( uint16_t addr, uint8_t data );
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//void discrete_exp0_mapper_wr( uint16_t addr, uint8_t data );
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//uint8_t emulate_nes_cpu_rd( uint8_t addrH, uint8_t addrL );
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uint8_t nes_cpu_rd( uint16_t addr );
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void nes_cpu_wr( uint16_t addr, uint8_t data );
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@ -22,8 +22,9 @@ function main ()
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--cart/mapper specific scripts
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--local curcart = require "scripts.nes.nrom"
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local curcart = require "scripts.nes.unrom"
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--local curcart = require "scripts.nes.bnrom"
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--local curcart = require "scripts.nes.unrom"
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local curcart = require "scripts.nes.bnrom"
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--local curcart = require "scripts.nes.cdream"
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--local curcart = require "scripts.nes.action53"
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--local curcart = require "scripts.nes.action53_tsop"
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@ -31,9 +32,28 @@ function main ()
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-- rv = dict.pinport( "DATA_SET", 0xAA )
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-- rv = dict.pinport( "DATA_RD" )
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-- rv = dict.io("IO_RESET")
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if rv then
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print(string.format("%X", rv))
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end
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--[[ --TEST GB power
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rv = dict.pinport( "CTL_ENABLE", "CIN" )
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rv = dict.pinport( "CTL_OP", "CIN")
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rv = dict.pinport( "CTL_SET_LO", "CIN")
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print("CIN low 5v GB")
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jtag.sleep(5)
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rv = dict.pinport( "CTL_SET_HI", "CIN")
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print("CIN high 3v GBA")
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jtag.sleep(90)
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rv = dict.pinport( "CTL_SET_LO", "CIN")
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print("CIN low 5v GB")
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jtag.sleep(10)
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rv = dict.pinport( "CTL_SET_HI", "CIN")
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print("CIN high 3v GBA")
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jtag.sleep(10)
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--]]
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--if rv then
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-- print(string.format("%X", rv))
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--end
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-- print(dict.io("EXP0_PULLUP_TEST"))
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--
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@ -132,7 +152,7 @@ function main ()
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--]]
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--[[
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---[[
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--test reading back CIC version
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dict.io("SWIM_INIT", "SWIM_ON_A0")
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if swim.start(true) then
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@ -143,7 +163,7 @@ function main ()
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print("ERROR trying to read back CIC signature stack data")
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end
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print("done flashing STM8 on A0")
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print("done reading STM8 stack on A0\n")
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dict.io("IO_RESET")
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--]]
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@ -157,10 +177,14 @@ function main ()
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--NROM
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--curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/ddug2.bin", "ignore/verifyout.bin")
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--UxROM
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curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/nomolosFINAL.prg", "ignore/verifyout.bin")
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--curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/nomolos.bin", "ignore/verifyout.bin")
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--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/nomolosFINAL.prg", "ignore/verifyout.bin")
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--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/owlia_revb.prg", "ignore/verifyout.bin")
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--BNROM
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--curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/lizard_v1.bin", "ignore/verifyout.bin")
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--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/lizard_v2.prg", "ignore/verifyout.bin")
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--curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/lizard_v2_fr.prg", "ignore/verifyout.bin")
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curcart.process( true, false, true, true, false, "ignore/dump.bin", "ignore/hh85.prg", "ignore/verifyout.bin")
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--COLOR DREAMS
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--curcart.process( true, false, true, true, true, "ignore/dump.bin", "ignore/multicart_mojontalesFINAL.prg", "ignore/verifyout.bin")
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--A53 PLCC
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--curcart.process( true, true, true, true, true, "ignore/dump.bin", "ignore/da53v2.prg", "ignore/verifyout.bin")
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--A53 tssop
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@ -200,6 +224,7 @@ function main ()
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elseif cart_console == "SNES" then
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snes_swimcart = nil
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--[[
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if swim.start(true) then
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--SWIM is now established and running at HIGH SPEED
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snes_swimcart = false --don't want to use SWIM pin to control flash /OE, use SNES RESET (EXP0) instead
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@ -222,6 +247,7 @@ function main ()
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else
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print("ERROR problem with STM8 CIC")
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end
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--]]
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dict.io("IO_RESET")
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dict.io("SNES_INIT")
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@ -232,6 +258,7 @@ function main ()
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local snes_mapping = "LOROM"
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--SNES detect if there's save ram and size
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---[[
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--SNES detect if able to read flash ID's
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if not snes.read_flashID(true) then
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print("ERROR unable to read flash ID")
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@ -257,8 +284,9 @@ function main ()
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-- erase.erase_snes( false )
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--open file
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local file
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-- file = assert(io.open("flash.bin", "rb"))
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file = assert(io.open("SF2_PTdump_capcomFINAL.bin", "rb"))
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---[[ file = assert(io.open("flash.bin", "rb"))
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--file = assert(io.open("SF2_PTdump_capcomFINAL.bin", "rb"))
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file = assert(io.open("ignore/MMXdump.bin", "rb"))
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--calculate checksum
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--local data = file:read("*all")
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@ -270,14 +298,21 @@ function main ()
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flash.flash_snes( file, true )
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--close file
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assert(file:close())
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--]]
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dict.io("IO_RESET")
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print("start swim")
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dict.io("SWIM_INIT", "SWIM_ON_A0")
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--flash final CIC code
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if swim.start(true) then
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--SWIM is now established and running at HIGH SPEED
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--swim.printCSR()
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snes_swimcart = false
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--snes_swimcart = false
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--print("main swimcart", snes_swimcart)
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swim.swim_test()
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--check if ROP set, allow clearing ROP and erasing CIC
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--blindly erase STM8 CIC for now by disabling ROP
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-- swim.disable_ROP_erase(true)
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@ -293,24 +328,27 @@ function main ()
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--write option bytes
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-- enable ROP, debug
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swim.write_optn_bytes( true, true )
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swim.write_optn_bytes( false, true )
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|
||||
-- reset STM8 CIC and end SWIM comms to it can execute what we just flashed
|
||||
swim.stop_and_reset()
|
||||
else
|
||||
print("ERROR problem with STM8 CIC")
|
||||
end
|
||||
--]]
|
||||
|
||||
-- --DUMPING:
|
||||
-- --create new file
|
||||
-- local file
|
||||
-- file = assert(io.open("snesdump.bin", "wb"))
|
||||
-- --dump cart into file
|
||||
-- -- swim.start()
|
||||
-- dump.dump_snes( file, snes_mapping, true )
|
||||
--
|
||||
-- --close file
|
||||
-- assert(file:close())
|
||||
--DUMPING:
|
||||
--create new file
|
||||
print("dumping SNES")
|
||||
snes.read_reset_vector(0, true)
|
||||
local file
|
||||
file = assert(io.open("snesdump.bin", "wb"))
|
||||
--dump cart into file
|
||||
-- swim.start()
|
||||
-- dump.dump_snes( file, snes_mapping, true )
|
||||
|
||||
--close file
|
||||
assert(file:close())
|
||||
|
||||
|
||||
--trick to do this at end while debugging so don't have to wait for it before starting
|
||||
|
|
@ -332,6 +370,7 @@ function main ()
|
|||
|
||||
end
|
||||
|
||||
|
||||
end
|
||||
|
||||
|
||||
|
|
|
|||
|
|
@ -136,7 +136,9 @@ local function process( test, read, erase, program, verify, dumpfile, flashfile,
|
|||
--find bank table in the rom
|
||||
--write bank table to all banks of cartridge
|
||||
--Lizard's bank table is at $FF94 so hard code that for now
|
||||
wr_bank_table(0xFF94, 16)
|
||||
--wr_bank_table(0xFF94, 16)
|
||||
--hh85 bank table at $FFE0
|
||||
wr_bank_table(0xFFE0, 16)
|
||||
|
||||
--flash cart
|
||||
flash.write_file( file, 512, "BxROM", "PRGROM", true )
|
||||
|
|
|
|||
|
|
@ -83,6 +83,7 @@ local function process( test, read, erase, program, verify, dumpfile, flashfile,
|
|||
dict.nes("NES_PPU_WR", 0x1555, 0x10)
|
||||
rv = dict.nes("NES_PPU_RD", 0x0000)
|
||||
|
||||
i = 0
|
||||
while ( rv ~= 0xFF ) do
|
||||
rv = dict.nes("NES_PPU_RD", 0x0000)
|
||||
i = i + 1
|
||||
|
|
|
|||
|
|
@ -136,6 +136,8 @@ local function process( test, read, erase, program, verify, dumpfile, flashfile,
|
|||
--write bank table to all banks of cartridge
|
||||
--Nomolos' bank table is at $CC84 so hard code that for now
|
||||
wr_bank_table(0xCC84, 32)
|
||||
--Owlia bank table
|
||||
--wr_bank_table(0xE473, 32)
|
||||
|
||||
--flash cart
|
||||
flash.write_file( file, 512, "UxROM", "PRGROM", true )
|
||||
|
|
|
|||
|
|
@ -138,7 +138,7 @@
|
|||
#define AxROM 7
|
||||
#define MMC2 9
|
||||
#define MMC4 10
|
||||
#define CDREAMS 11
|
||||
#define CDREAM 11
|
||||
#define A53 28
|
||||
#define UNROM512 30
|
||||
#define EZNSF 31
|
||||
|
|
|
|||
|
|
@ -37,6 +37,8 @@
|
|||
// A15 decoded to enable /ROMSEL as it should
|
||||
#define NES_CPU_WR 0x02
|
||||
|
||||
//#define DISCRETE_EXP0_MAPPER_WR 0x03
|
||||
|
||||
//=============================================================================================
|
||||
// OPCODES WITH OPERAND AND RETURN VALUE plus SUCCESS/ERROR_CODE
|
||||
//=============================================================================================
|
||||
|
|
|
|||
Loading…
Reference in New Issue